v_cmp_class_f64 GPU Native ISA AMD Vector

Comparison

v_cmp_class_f64

Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a double-precision float, and set the…

Encoding

Binary Layout (AMD CDNA 5)
0111110
31:25
01111111
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOPC layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 127 in OP rebuilds 0x7CFE0000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 18), AMD CDNA 3 (opcode 18), AMD CDNA 2 (opcode 18), AMD CDNA 1 (opcode 18), AMD RDNA 2 (opcode 168), AMD RDNA 1 (opcode 168). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format VOPC
Width 32 bits
Opcode 127
Identifier 0x7CFE0000

Operands

  • vcc
    Written. Written in the assembly; this encoding has no field for it. 64-bit vector condition code. Data format: 64-bit mask value, read or written to a consecutive run of GPRs. The first GPR contains the least significant dword of the data. This format is generally used for lane masks and may be truncated to 32 bits when running in wave32 mode. Scalar operands with the M64 format do not have an alignment restriction when running in wave32 mode. (OPR_VCC, FMT_NUM_M64)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 64-bit double-precision floating point value. (OPR_SRC, FMT_NUM_F64)
  • VSRC1
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOPC encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Comparison

Reference

AMDGPU / GFX ISA

Description

Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a double-precision float, and set the per-lane condition code to the result. Store the result into VCC or a scalar register. The function reports true if the floating point value is any of the numeric types selected in the 10 bit mask according to the following list: S1.u[0] value is a signaling NAN. S1.u[1] value is a quiet NAN. S1.u[2] value is negative infinity. S1.u[3] value is a negative normal value. S1.u[4] value is a negative denormal value. S1.u[5] value is negative zero. S1.u[6] value is positive zero. S1.u[7] value is a positive denormal value. S1.u[8] value is a positive normal value. S1.u[9] value is positive infinity.

Semantics

declare result : 1'U; if isSignalNAN(S0.f64) then result = S1.u32[0] elsif isQuietNAN(S0.f64) then result = S1.u32[1] elsif exponent(S0.f64) == 2047 then // +-INF result = S1.u32[sign(S0.f64) ? 2 : 9] elsif exponent(S0.f64) > 0 then // +-normal value result = S1.u32[sign(S0.f64) ? 3 : 8] elsif abs(S0.f64) > 0.0 then // +-denormal value result = S1.u32[sign(S0.f64) ? 4 : 7] else // +-0.0 result = S1.u32[sign(S0.f64) ? 5 : 6] endif; D0.u64[laneId] = result; // D0 = VCC in VOPC encoding.

Example

v_cmp_class_f64 vcc, -1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources