s_cmp_lg_u64 GPU Native ISA AMD Scalar

Comparison

s_cmp_lg_u64

Set SCC to 1 iff the first scalar input is less than or greater than the second scalar input.

Encoding

Binary Layout (AMD CDNA 5)
101111110
31:23
0010001
22:16
SSRC1
15:8
SSRC0
7:0
 

The ENC_SOPC layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 17 in OP rebuilds 0xBF110000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 19), AMD CDNA 3 (opcode 19), AMD CDNA 2 (opcode 19), AMD CDNA 1 (opcode 19), AMD RDNA 2 (opcode 19), AMD RDNA 1 (opcode 19). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOPC
Width 32 bits
Opcode 17
Identifier 0xBF110000

Operands

  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Unsigned 64-bit integral data. (OPR_SSRC, FMT_NUM_U64)
  • SSRC1
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Unsigned 64-bit integral data. (OPR_SSRC, FMT_NUM_U64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPC encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Comparison

Reference

AMDGPU / GFX ISA

Semantics

SCC = S0.u64 <> S1.u64

Example

s_cmp_lg_u64 s[0:1], 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources