s_cmp_u_f16 GPU Native ISA AMD Scalar

Comparison

s_cmp_u_f16

Set SCC to 1 iff the first scalar input is not orderable to the second scalar input.

Encoding

Binary Layout (AMD CDNA 5)
101111110
31:23
1011000
22:16
SSRC1
15:8
SSRC0
7:0
 

The ENC_SOPC layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 88 in OP rebuilds 0xBF580000, an identifier AMD lists for this encoding. The same in the other 2 generations that define it.

Format SOPC
Width 32 bits
Opcode 88
Identifier 0xBF580000

Operands

  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: 16-bit half-precision floating point value. (OPR_SSRC, FMT_NUM_F16)
  • SSRC1
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: 16-bit half-precision floating point value. (OPR_SSRC, FMT_NUM_F16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPC encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Comparison

Reference

AMDGPU / GFX ISA

Example

s_cmp_u_f16 0, s2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx1150_asm_salu_float.s). Not from an AMD document, and not authored here.

Sources