s_set_gpr_idx_on GPU Native ISA AMD Scalar

Comparison

s_set_gpr_idx_on

Enable GPR indexing mode.

Encoding

Binary Layout (AMD CDNA 4)
101111110
31:23
0010001
22:16
SSRC1
15:8
SSRC0
7:0
 

The ENC_SOPC layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 17 in OP rebuilds 0xBF110000, an identifier AMD lists for this encoding. The same in the other 3 generations that define it.

Format SOPC
Width 32 bits
Opcode 17
Identifier 0xBF110000

Operands

  • SSRC0
    Read. N/A Data format: N/A (OPR_SSRC, FMT_NUM_B32)
  • SSRC1
    Read. 4-bit integer constant. Data format: N/A (OPR_SIMM4, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPC encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Comparison

Reference

AMDGPU / GFX ISA

Example

s_set_gpr_idx_on 0, 0x0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx8_asm_sopc.s). Not from an AMD document, and not authored here.

Sources