s_cmp_eq_i32 GPU Native ISA AMD Scalar

Comparison

s_cmp_eq_i32 S0, S1

Scalar signed-32-bit equality compare, result written to SCC.

Encoding

Binary Layout (AMD CDNA 5)
101111110
31:23
0000000
22:16
SSRC1
15:8
SSRC0
7:0
 

The ENC_SOPC layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 0 in OP rebuilds 0xBF000000, an identifier AMD lists for this encoding. The same in the other 9 generations that define it.

Format SOPC
Width 32 bits
Opcode 0
Identifier 0xBF000000
Execution Unit Scalar ALU
Register Classes SGPR

Operands

  • S0
    First source SGPR/constant
  • S1
    Second source SGPR/constant

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Compare ↗
equivalent with restrictions
setp (PTX)

Related

More in Comparison

Reference

AMDGPU / GFX ISA

Description

Set SCC to 1 iff the first scalar input is equal to the second scalar input.

Semantics

SCC = (S0.i32 == S1.i32).

Example

s_cmp_eq_i32  s0, s1   // SCC = (s0 == s1)

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources