s_cmp_eq_i32 GPU Native ISA AMD Scalar

S CMP EQ I32 Comparison

s_cmp_eq_i32 S0, S1

Scalar signed-32-bit equality compare, result written to SCC.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (SOPC) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format SOPC
Width 32 bits
Execution Unit Scalar ALU
Register Classes SGPR

Operands

  • S0
    First source SGPR/constant
  • S1
    Second source SGPR/constant

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Compare ↗
equivalent with restrictions
setp (PTX)

Related

More in Comparison

Reference

AMDGPU / GFX ISA

Description

Set SCC to 1 iff the first scalar input is equal to the second scalar input.

Semantics

SCC = (S0.i32 == S1.i32).

Example

s_cmp_eq_i32  s0, s1   // SCC = (s0 == s1)

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources