setp GPU Virtual ISA NVIDIA

Set Predicate Comparison and Selection Instructions

setp.CmpOp.type p, a, b;

Compare two operands and write the boolean result to a predicate register.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 1.0
Minimum Target sm_10

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
setp.CmpOp.type p, a, b; s32, s64, u32, u64, f32, f64 sm_10 Comparison writing a predicate register, consumed by @p-guarded instructions.

Operands

  • p
    Destination predicate register
  • a
    First operand
  • b
    Second operand

At a Glance

Data Types f32, f64, s32, s64, u32, u64

Related AMDGPU Concepts

Compare ↗
equivalent with restrictions
v_cmp_eq_f32 (AMDGPU)
s_cmp_eq_i32 (AMDGPU)

Reference

NVIDIA PTX ISA

Description

Compares two values and combines the result with another predicate value by applying a Boolean operator. This result is written to the first destination operand. A related value computed using the complement of the compare result is written to the second destination operand. Applies to all numeric types. Operands a and b have type.type; operands p, q, and c have type.pred. The sink symbol ‘_’ may be used in place of any one of the destination operands.

Semantics

p = CmpOp(a, b).

Examples

setp.lt.and.s32  p|q,a,b,r;
@q  setp.eq.u32      p,i,n;

setp.lt.and.f16x2  p|q,a,b,r;
@q  setp.eq.f16    p,i,n;

setp.gt.or.bf16x2  u|v,c,d,s;
@q  setp.eq.bf16   u,j,m;

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources