set GPU Virtual ISA NVIDIA

Set (Compare and Produce Value) Comparison and Selection Instructions

set.CmpOp.dtype.stype d, a, b;

Compare two operands and write a numeric (not predicate) 0/1 or all-ones/all-zeros result.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 1.0
Minimum Target sm_10

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
set.CmpOp.dtype.stype d, a, b; u32, s32, f32 sm_10 Comparison producing a value, useful when the result feeds arithmetic rather than a guarded branch.

Operands

  • d
    Destination register
  • a
    First operand
  • b
    Second operand

At a Glance

Data Types f32, s32, u32

Related

More in Comparison and Selection Instructions

Reference

NVIDIA PTX ISA

Description

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. Result of this computation is written in destination register in the following way: If result is True, 0xffffffff is written for destination types.u32 /.s32. 0xffff is written for destination types.u16 /.s16. 1.0 in target precision floating point format is written for destination type.f16,.bf16. If result is False, 0x0 is written for all integer destination types. (see the official PTX ISA docs for the full description)

Semantics

d = CmpOp(a, b) ? (all-ones or 1) : 0, encoding depends on dtype.

Examples

@p  set.lt.and.f32.s32  d,a,b,r;
    set.eq.u32.u32      d,i,n;

set.lt.and.f16.f16  d,a,b,r;
set.eq.f16x2.f16x2  d,i,n;
set.eq.u32.f16x2    d,i,n;
set.lt.and.u16.f16  d,a,b,r;
set.ltu.or.bf16.f16    d,u,v,s;
set.equ.bf16x2.bf16x2  d,j,m;
// (truncated - see the official PTX ISA docs for the full example)

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources