v_cmp_gt_u64 GPU Native ISA AMD Vector
Comparison
Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register.
Encoding
The ENC_VOPC layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 92 in OP rebuilds 0x7CB80000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 236), AMD CDNA 3 (opcode 236), AMD CDNA 2 (opcode 236), AMD CDNA 1 (opcode 236), AMD RDNA 2 (opcode 228), AMD RDNA 1 (opcode 228). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.
Operands
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vcc
Written. Written in the assembly; this encoding has no field for it. 64-bit vector condition code. Data format: 64-bit mask value, read or written to a consecutive run of GPRs. The first GPR contains the least significant dword of the data. This format is generally used for lane masks and may be truncated to 32 bits when running in wave32 mode. Scalar operands with the M64 format do not have an alignment restriction when running in wave32 mode. (OPR_VCC, FMT_NUM_M64) -
SRC0
Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Unsigned 64-bit integral data. (OPR_SRC, FMT_NUM_U64) -
VSRC1
Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Unsigned 64-bit integral data. (OPR_VGPR, FMT_NUM_U64)
In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOPC encoding (AMD CDNA 5).
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Comparison
Reference
Semantics
Example
v_cmp_gt_u64 vcc, -1, v[2:3]A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 257. - LLVM MC assembler tests for AMDGPU ↗ - LLVM Project
- AMD Machine-Readable GPU ISA Specification ↗ - Advanced Micro Devices, Inc.