AMDGPU / GFX Instructions GPU Native ISA AMD
2442 instructions - showing 100 per page, page 12 of 25 - AMDGPU/GFX is AMD's native, low-level
GPU instruction set family, assembled directly with no virtual intermediate layer. Supported
instructions and their exact encodings vary by GFX compatibility target (e.g.
gfx942, gfx1100). Scalar instructions execute once per wavefront on
the Scalar ALU; vector instructions execute per-lane on the Vector ALU, gated by the EXEC mask.
How AMDGPU compares to the other GPU ISA
Decode a AMDGPU instruction word
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| Mnemonic | Syntax | Format | GFX Targets | Unit | Summary |
|---|---|---|---|---|---|
| s_nor_b32 | s_nor_b32 | SOP2 | gfx1100 | Calculate bitwise NOR on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero. | |
| s_nor_b64 | s_nor_b64 | SOP2 | gfx1100 | Calculate bitwise NOR on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero. | |
| s_nor_saveexec_b32 | s_nor_saveexec_b32 | SOP1 | gfx1100 | Calculate bitwise NOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is… | |
| s_nor_saveexec_b64 | s_nor_saveexec_b64 | SOP1 | gfx1100 | Calculate bitwise NOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is… | |
| s_not_b32 | s_not_b32 | SOP1 | gfx1100 | Calculate bitwise negation on a scalar input, store the result into a scalar register and set SCC iff the result is nonzero. | |
| s_not_b64 | s_not_b64 | SOP1 | gfx1100 | Calculate bitwise negation on a scalar input, store the result into a scalar register and set SCC iff the result is nonzero. | |
| s_or_b32 | s_or_b32 | SOP2 | gfx1100 | Calculate bitwise OR on two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero. | |
| s_or_b64 | s_or_b64 | SOP2 | gfx1100 | Calculate bitwise OR on two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero. | |
| s_or_not0_saveexec_b32 | s_or_not0_saveexec_b32 | SOP1 | gfx1100 | Calculate bitwise OR on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the… | |
| s_or_not0_saveexec_b64 | s_or_not0_saveexec_b64 | SOP1 | gfx1100 | Calculate bitwise OR on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the… | |
| s_or_not1_b32 | s_or_not1_b32 | SOP2 | gfx1100 | Calculate bitwise OR with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is… | |
| s_or_not1_b64 | s_or_not1_b64 | SOP2 | gfx1100 | Calculate bitwise OR with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is… | |
| s_or_not1_saveexec_b32 | s_or_not1_saveexec_b32 | SOP1 | gfx1100 | Calculate bitwise OR on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the… | |
| s_or_not1_saveexec_b64 | s_or_not1_saveexec_b64 | SOP1 | gfx1100 | Calculate bitwise OR on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the… | |
| s_or_saveexec_b32 | s_or_saveexec_b32 | SOP1 | gfx1100 | Calculate bitwise OR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is… | |
| s_or_saveexec_b64 | s_or_saveexec_b64 | SOP1 | gfx1100 | Calculate bitwise OR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is… | |
| s_orn1_saveexec_b32 | s_orn1_saveexec_b32 | SOP1 | gfx1100 | Calculate bitwise OR on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the… | |
| s_orn1_saveexec_b64 | s_orn1_saveexec_b64 | SOP1 | gfx1100 | Calculate bitwise OR on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the… | |
| s_orn2_b32 | s_orn2_b32 | SOP2 | gfx1100 | Calculate bitwise OR with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is… | |
| s_orn2_b64 | s_orn2_b64 | SOP2 | gfx1100 | Calculate bitwise OR with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is… | |
| s_orn2_saveexec_b32 | s_orn2_saveexec_b32 | SOP1 | gfx1100 | Calculate bitwise OR on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the… | |
| s_orn2_saveexec_b64 | s_orn2_saveexec_b64 | SOP1 | gfx1100 | Calculate bitwise OR on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the… | |
| s_pack_hh_b32_b16 | s_pack_hh_b32_b16 | SOP2 | gfx1100 | Pack two 16-bit scalar values into a scalar register. | |
| s_pack_hl_b32_b16 | s_pack_hl_b32_b16 | SOP2 | gfx1100 | Pack two 16-bit scalar values into a scalar register. | |
| s_pack_lh_b32_b16 | s_pack_lh_b32_b16 | SOP2 | gfx1100 | Pack two 16-bit scalar values into a scalar register. | |
| s_pack_ll_b32_b16 | s_pack_ll_b32_b16 | SOP2 | gfx1100 | Pack two 16-bit scalar values into a scalar register. | |
| s_prefetch_data | s_prefetch_data | SMEM | Prefetch data into the scalar data cache, relative to a base address provided. | ||
| s_prefetch_data_pc_rel | s_prefetch_data_pc_rel | SMEM | Prefetch data into the scalar data cache, relative to the current PC address. | ||
| s_prefetch_inst | s_prefetch_inst | SMEM | Prefetch instructions into the shader instruction cache, relative to a base address provided. | ||
| s_prefetch_inst_pc_rel | s_prefetch_inst_pc_rel | SMEM | Prefetch instructions into the shader instruction cache, relative to the current PC address. | ||
| s_quadmask_b32 | s_quadmask_b32 | SOP1 | gfx1100 | Reduce a pixel mask from the scalar input into a quad mask, store the result in a scalar register and set SCC iff the result is nonzero. | |
| s_quadmask_b64 | s_quadmask_b64 | SOP1 | gfx1100 | Reduce a pixel mask from the scalar input into a quad mask, store the result in a scalar register and set SCC iff the result is nonzero. | |
| s_rfe_b64 | s_rfe_b64 | SOP1 | gfx1100 | Return from the exception handler. | |
| s_rfe_i64 | s_rfe_i64 | SOP1 | gfx1100 | AMDGPU SOP1 scalar instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | |
| s_rfe_restore_b64 | s_rfe_restore_b64 | SOP2 | Return from exception handler and continue. This instruction may only be used within a trap handler. | ||
| s_rndne_f16 | s_rndne_f16 | SOP1 | gfx1100 | Round the half-precision float input to the nearest even integer and store the result in floating point format into a scalar register. | |
| s_rndne_f32 | s_rndne_f32 | SOP1 | gfx1100 | Round the single-precision float input to the nearest even integer and store the result in floating point format into a scalar register. | |
| s_round_mode | s_round_mode | SOPP | Set floating point round mode using an immediate constant. | ||
| s_scratch_load_dword | s_scratch_load_dword | SMEM | Load 32 bits of data from the scalar scratch aperture into a scalar register. | ||
| s_scratch_load_dwordx2 | s_scratch_load_dwordx2 | SMEM | Load 64 bits of data from the scalar scratch aperture into a scalar register. | ||
| s_scratch_load_dwordx4 | s_scratch_load_dwordx4 | SMEM | Load 128 bits of data from the scalar scratch aperture into a scalar register. | ||
| s_scratch_store_dword | s_scratch_store_dword | SMEM | Store 32 bits of data from a scalar register into the scalar scratch aperture. | ||
| s_scratch_store_dwordx2 | s_scratch_store_dwordx2 | SMEM | Store 64 bits of data from a scalar register into the scalar scratch aperture. | ||
| s_scratch_store_dwordx4 | s_scratch_store_dwordx4 | SMEM | Store 128 bits of data from a scalar register into the scalar scratch aperture. | ||
| s_sendmsg | s_sendmsg | SOPP | gfx1100 | Send a message upstream to graphics control hardware. SIMM16[9:0] contains the message type. | |
| s_sendmsg_rtn_b32 | s_sendmsg_rtn_b32 | SOP1 | Send a message to upstream control hardware. | ||
| s_sendmsg_rtn_b64 | s_sendmsg_rtn_b64 | SOP1 | Send a message to upstream control hardware. | ||
| s_sendmsghalt | s_sendmsghalt | SOPP | gfx1100 | Send a message to upstream control hardware and then HALT the wavefront; see S_SENDMSG for details. | |
| s_set_gpr_idx_idx | s_set_gpr_idx_idx | SOP1 | Set the index used in vector GPR indexing. S_SET_GPR_IDX_ON, S_SET_GPR_IDX_OFF, S_SET_GPR_IDX_MODE and S_SET_GPR_IDX_IDX are related instructions. | ||
| s_set_gpr_idx_mode | s_set_gpr_idx_mode | SOPP | Modify the mode used for vector GPR indexing. | ||
| s_set_gpr_idx_off | s_set_gpr_idx_off | SOPP | Clear GPR indexing mode. | ||
| s_set_gpr_idx_on | s_set_gpr_idx_on | SOPC | Enable GPR indexing mode. | ||
| s_set_inst_prefetch_distance | s_set_inst_prefetch_distance | SOPP | gfx1100 | Change instruction prefetch mode. This controls how many cachelines ahead of the current PC the shader attempts to prefetch. | |
| s_set_pc_i64 | s_set_pc_i64 | SOP1 | gfx1100 | AMDGPU SOP1 scalar instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | |
| s_set_valu_coexec_mode | s_set_valu_coexec_mode | SOPP | Set the vector ALU co-execution mode to the value encoded in SIMM16[1:0] for the next VALU instruction. | ||
| s_set_vgpr_msb | s_set_vgpr_msb | SOPP | AMDGPU SOPP scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| s_sethalt | s_sethalt | SOPP | gfx1100 | Set or clear the HALT status bit. | |
| s_setkill | s_setkill | SOPP | gfx1100 | Kill this wave if the least significant bit of the immediate constant is 1. Used primarily for debugging kill wave host command behavior. | |
| s_setpc_b64 | s_setpc_b64 | SOP1 | gfx1100 | Jump to an address specified in a scalar register. The argument is a byte address of the instruction to jump to. | |
| s_setprio | s_setprio | SOPP | gfx1100 | Change wave user priority. | |
| s_setprio_inc_wg | s_setprio_inc_wg | SOPP | AMDGPU SOPP scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| s_setreg_b32 | s_setreg_b32 | SOPK | Write some or all of the LSBs of source argument into a hardware register. | ||
| s_setreg_imm32_b32 | s_setreg_imm32_b32 | SOPK | Write some or all of the LSBs of a 32-bit literal constant into a hardware register; this instruction requires a 32-bit literal constant. | ||
| s_setvskip | s_setvskip | SOPC | Enables or disables VSKIP mode. | ||
| s_sext_i32_i16 | s_sext_i32_i16 | SOP1 | gfx1100 | Sign extend a signed 16 bit scalar input to 32 bits and store the result into a scalar register. | |
| s_sext_i32_i8 | s_sext_i32_i8 | SOP1 | gfx1100 | Sign extend a signed 8 bit scalar input to 32 bits and store the result into a scalar register. | |
| s_sleep | s_sleep | SOPP | gfx1100 | Cause a wave to sleep for up to ~8000 clocks. | |
| s_sleep_var | s_sleep_var | SOP1 | Cause a wave to sleep for up to ~8000 clocks, or to sleep until an external event wakes the wave up. | ||
| s_soft_wait_bvhcnt | s_soft_wait_bvhcnt | SOPP | AMDGPU SOPP scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| s_soft_wait_dscnt | s_soft_wait_dscnt | SOPP | AMDGPU SOPP scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| s_soft_wait_kmcnt | s_soft_wait_kmcnt | SOPP | AMDGPU SOPP scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| s_soft_wait_loadcnt | s_soft_wait_loadcnt | SOPP | AMDGPU SOPP scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| s_soft_wait_samplecnt | s_soft_wait_samplecnt | SOPP | AMDGPU SOPP scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| s_soft_wait_storecnt | s_soft_wait_storecnt | SOPP | AMDGPU SOPP scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| s_soft_waitcnt | s_soft_waitcnt | SOPP | AMDGPU SOPP scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| s_soft_waitcnt_vscnt | s_soft_waitcnt_vscnt | SOPK | AMDGPU SOPK scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| s_store_dword | s_store_dword | SMEM | Store 32 bits of data from a scalar register into the scalar memory. | ||
| s_store_dwordx2 | s_store_dwordx2 | SMEM | Store 64 bits of data from a scalar register into the scalar memory. | ||
| s_store_dwordx4 | s_store_dwordx4 | SMEM | Store 128 bits of data from a scalar register into the scalar memory. | ||
| s_sub_co_ci_u32 | s_sub_co_ci_u32 | SOP2 | gfx1100 | Subtract the second unsigned 32-bit integer input from the first input, subtract the carry-in bit, store the result into a scalar register and store… | |
| s_sub_co_i32 | s_sub_co_i32 | SOP2 | gfx1100 | Subtract the second signed 32-bit integer input from the first input, store the result into a scalar register and store the carry-out bit into SCC. | |
| s_sub_co_u32 | s_sub_co_u32 | SOP2 | gfx1100 | Subtract the second unsigned 32-bit integer input from the first input, store the result into a scalar register and store the carry-out bit into SCC. | |
| s_sub_f16 | s_sub_f16 | SOP2 | gfx1100 | Subtract the second floating point input from the first input and store the result in a scalar register. | |
| s_sub_f32 | s_sub_f32 | SOP2 | gfx1100 | Subtract the second floating point input from the first input and store the result in a scalar register. | |
| s_sub_i32 | s_sub_i32 | SOP2 | gfx1100 | Subtract the second signed 32-bit integer input from the first input, store the result into a scalar register and store the carry-out bit into SCC. | |
| s_sub_nc_u64 | s_sub_nc_u64 | SOP2 | Subtract the second unsigned 64-bit integer input from the first input and store the result into a scalar register. | ||
| s_sub_u32 | s_sub_u32 SDST, S0, S1 | SOP2 | gfx942, gfx1100 | Scalar ALU | Subtract two 32-bit unsigned scalar operands, wavefront-uniform. |
| s_sub_u64 | s_sub_u64 | SOP2 | AMDGPU SOP2 scalar instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| s_subb_u32 | s_subb_u32 | SOP2 | gfx1100 | Subtract the second unsigned 32-bit integer input from the first input, subtract the carry-in bit, store the result into a scalar register and store… | |
| s_subvector_loop_begin | s_subvector_loop_begin | SOPK | gfx1100 | Begin execution of a subvector block of code. | |
| s_subvector_loop_end | s_subvector_loop_end | SOPK | gfx1100 | End execution of a subvector block of code. | |
| s_swap_pc_i64 | s_swap_pc_i64 | SOP1 | gfx1100 | AMDGPU SOP1 scalar instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | |
| s_swappc_b64 | s_swappc_b64 | SOP1 | gfx1100 | Store the address of the next instruction to a scalar register and then jump to an address specified in the scalar input. | |
| s_trap | s_trap | SOPP | gfx1100 | Enter the trap handler. | |
| s_trunc_f16 | s_trunc_f16 | SOP1 | gfx1100 | Compute the integer part of a half-precision float input using round toward zero semantics and store the result in floating point format into a… | |
| s_trunc_f32 | s_trunc_f32 | SOP1 | gfx1100 | Compute the integer part of a single-precision float input using round toward zero semantics and store the result in floating point format into a… | |
| s_ttracedata | s_ttracedata | SOPP | gfx1100 | Send M0 as user data to the thread trace stream. | |
| s_ttracedata_imm | s_ttracedata_imm | SOPP | Send SIMM16[7:0] as user data to the thread trace stream. | ||
| s_version | s_version | SOPK | Do nothing. This opcode is used to specify the microcode version for tools that interpret shader microcode. | ||
| s_wait_alu | s_wait_alu | SOPP | gfx1100 | Wait for one or more ALU-centric counters to fall below specified values. |
Source
Normalized from AMD's official ROCm documentation, with the LLVM AMDGPU backend documentation as supplementary compiler-target information. ROCm documentation ↗