s_prefetch_inst GPU Native ISA AMD Scalar

Scalar Memory

s_prefetch_inst

Prefetch instructions into the shader instruction cache, relative to a base address provided.

Encoding

Binary Layout (AMD CDNA 5)
SOFFSET
63:57
SCALE_OFFSET
56
IOFFSET
55:32
111101
31:26
unassigned
25
TH
24:23
SCOPE
22:21
NV
20
unassigned
19
100100
18:13
SDATA
12:6
SBASE
5:0
 

The ENC_SMEM layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 36 in OP rebuilds 0x00000000F4048000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD RDNA 4 (field layout).

Format SMEM
Width 64 bits
Opcode 36
Identifier 0x00000000F4048000

Operands

  • SBASE
    Read. Any scalar GPR operand including VCC and NULL. Data format: 64 bits of arbitrary data. (OPR_SREG, FMT_NUM_B64)
  • IOFFSET
    Read. 24-bit integer constant. Data format: 32 bits of arbitrary data. (OPR_SIMM24, FMT_NUM_B32)
  • SOFFSET
    Read. Operand is a scalar memory offset, which may come from a scalar GPR or M0. Data format: 32 bits of arbitrary data. (OPR_SMEM_OFFSET_NOK, FMT_NUM_B32)
  • SDATA
    Read. 5-bit integer constant. Data format: 32 bits of arbitrary data. (OPR_SIMM5, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SMEM encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Memory

Reference

AMDGPU / GFX ISA

Example

s_prefetch_inst s[12:13], 16, s4, 2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx12_asm_smem.s). Not from an AMD document, and not authored here.

Sources