s_get_waveid_in_workgroup GPU Native ISA AMD Scalar

Scalar Memory

s_get_waveid_in_workgroup

Return the wave's ID within a workgroup 0-(N-1).

Encoding

Binary Layout (AMD RDNA 1)
SOFFSET
63:57
unassigned
56:53
OFFSET
52:32
111101
31:26
00101010
25:18
unassigned
17
GLC
16
unassigned
15
DLC
14
unassigned
13
SDATA
12:6
SBASE
5:0
 

The ENC_SMEM layout from AMD's machine-readable ISA specification (AMD RDNA 1). Opcode 42 in OP rebuilds 0x00000000F4A80000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. No other generation in the specification defines this instruction.

Format SMEM
Width 64 bits
Opcode 42
Identifier 0x00000000F4A80000

Operands

  • SDATA
    Written. N/A Data format: N/A (OPR_SREG, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SMEM encoding (AMD RDNA 1).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Memory

Reference

AMDGPU / GFX ISA

Description

Return the wave's ID within a workgroup 0-(N-1). Return zero if wave is not in a workgroup. ID reflects the order in which waves were created within each workgroup.

Example

s_get_waveid_in_workgroup s0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources