s_buffer_load_b512 GPU Native ISA AMD Scalar

Scalar Memory

s_buffer_load_b512

Load 512 bits of data from a scalar buffer surface into a scalar register.

Also written as s_buffer_load_dwordx16. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 5)
SOFFSET
63:57
SCALE_OFFSET
56
IOFFSET
55:32
111101
31:26
unassigned
25
TH
24:23
SCOPE
22:21
NV
20
unassigned
19
010100
18:13
SDATA
12:6
SBASE
5:0
 

The ENC_SMEM layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 20 in OP rebuilds 0x00000000F4028000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD RDNA 4 (field layout), AMD RDNA 3.5 (opcode 12, field layout), AMD RDNA 3 (opcode 12, field layout).

Format SMEM
Width 64 bits
Opcode 20
Identifier 0x00000000F4028000

Operands

  • SDATA
    Written. Any scalar GPR operand including VCC and NULL. Data format: Value can be anything. (OPR_SREG, FMT_ANY)
  • SBASE
    Read. Any scalar GPR operand including VCC and NULL. Data format: 128-bit buffer resource constant. (OPR_SREG, FMT_RSRC_SCALAR)
  • SOFFSET
    Read. Operand is a scalar memory offset, which may come from a scalar GPR, from M0 or from a 24-bit immediate constant. Data format: 32 bits of arbitrary data. (OPR_SMEM_OFFSET, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SMEM encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Memory

Reference

AMDGPU / GFX ISA

Example

s_buffer_load_b512 s[20:35], s[4:7], s0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx12_asm_smem.s). Not from an AMD document, and not authored here.

Sources