s_dcache_wb GPU Native ISA AMD Scalar

Scalar Memory

s_dcache_wb

Write back dirty data in the scalar (L0) data cache.

Encoding

Binary Layout (AMD CDNA 4)
SOFFSET
63:57
unassigned
56:53
OFFSET
52:32
110000
31:26
00100001
25:18
IMM
17
GLC
16
NV
15
SOFFSET_EN
14
unassigned
13
SDATA
12:6
SBASE
5:0
 

The ENC_SMEM layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 33 in OP rebuilds 0x00000000C0840000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. The same in the other 3 generations that define it.

Format SMEM
Width 64 bits
Opcode 33
Identifier 0x00000000C0840000

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Memory

Reference

AMDGPU / GFX ISA

Sources