s_load_dword GPU Native ISA AMD Scalar

S LOAD DWORD Scalar Memory

s_load_dword SDST, SBASE, offset

Load one 32-bit dword from memory into a scalar register, wavefront-uniform.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (SMEM) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format SMEM
Width 32 bits
Execution Unit Scalar Memory Unit
Register Classes SGPR
Memory Segment uniform/constant

Operands

  • SDST
    Destination SGPR
  • SBASE
    Base address (SGPR pair)
  • offset
    Immediate or SGPR offset

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Uniform (Read-Only) Load ↗
equivalent with restrictions
ldu (PTX)

Related

More in Scalar Memory

Reference

AMDGPU / GFX ISA

Description

Load 32 bits of data from the scalar memory into a scalar register.

Semantics

SDST = *(SBASE + offset); intended for uniform (not per-lane-varying) addresses such as descriptors and kernel arguments.

Example

s_load_dword  s4, s[8:9], 0x10   // s4 = *(s[8:9] + 0x10)

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources