s_load_dword GPU Native ISA AMD Scalar

Scalar Memory

s_load_dword SDST, SBASE, offset

Load one 32-bit dword from memory into a scalar register, wavefront-uniform.

Also written as s_load_b32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
SOFFSET
63:57
unassigned
56:53
OFFSET
52:32
110000
31:26
00000000
25:18
IMM
17
GLC
16
NV
15
SOFFSET_EN
14
unassigned
13
SDATA
12:6
SBASE
5:0
 

The ENC_SMEM layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 0 in OP rebuilds 0x00000000C0000000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD RDNA 2 (field layout), AMD RDNA 1 (field layout). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1.

Format SMEM
Width 64 bits
Opcode 0
Identifier 0x00000000C0000000
Execution Unit Scalar Memory Unit
Register Classes SGPR
Memory Segment uniform/constant

Operands

  • SDST
    Destination SGPR
  • SBASE
    Base address (SGPR pair)
  • offset
    Immediate or SGPR offset

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Uniform (Read-Only) Load ↗
equivalent with restrictions
ldu (PTX)

Related

More in Scalar Memory

Reference

AMDGPU / GFX ISA

Description

Load 32 bits of data from the scalar memory into a scalar register.

Semantics

SDST = *(SBASE + offset); intended for uniform (not per-lane-varying) addresses such as descriptors and kernel arguments.

Example

s_load_dword  s4, s[8:9], 0x10   // s4 = *(s[8:9] + 0x10)

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources