s_load_dwordx16 GPU Native ISA AMD Scalar

Scalar Memory

s_load_dwordx16

Load 512 bits of data from the scalar memory into a scalar register.

Also written as s_load_b512. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
SOFFSET
63:57
unassigned
56:53
OFFSET
52:32
110000
31:26
00000100
25:18
IMM
17
GLC
16
NV
15
SOFFSET_EN
14
unassigned
13
SDATA
12:6
SBASE
5:0
 

The ENC_SMEM layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 4 in OP rebuilds 0x00000000C0100000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD RDNA 2 (field layout), AMD RDNA 1 (field layout). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1.

Format SMEM
Width 64 bits
Opcode 4
Identifier 0x00000000C0100000

Operands

  • SDATA
    Written. N/A Data format: Value can be anything. (OPR_SREG, FMT_ANY)
  • SBASE
    Read. N/A Data format: 64-bit virtual memory address. (OPR_SREG, FMT_BUF)
  • SOFFSET
    Read. N/A Data format: N/A (OPR_SMEM_OFFSET, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SMEM encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Memory

Reference

AMDGPU / GFX ISA

Example

s_load_dwordx16 s[20:35], vcc, s0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx10_asm_smem.s). Not from an AMD document, and not authored here.

Sources