s_dcache_inv GPU Native ISA AMD Scalar

Scalar Memory

s_dcache_inv

Invalidate the scalar (L0) data cache.

Encoding

Binary Layout (AMD CDNA 5)
SOFFSET
63:57
SCALE_OFFSET
56
IOFFSET
55:32
111101
31:26
unassigned
25
TH
24:23
SCOPE
22:21
NV
20
unassigned
19
100001
18:13
SDATA
12:6
SBASE
5:0
 

The ENC_SMEM layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 33 in OP rebuilds 0x00000000F4042000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 4 (opcode 32, field layout), AMD CDNA 3 (opcode 32, field layout), AMD CDNA 2 (opcode 32, field layout), AMD CDNA 1 (opcode 32, field layout), AMD RDNA 4 (field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (opcode 32, field layout), AMD RDNA 1 (opcode 32, field layout).

Format SMEM
Width 64 bits
Opcode 33
Identifier 0x00000000F4042000

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Memory

Reference

AMDGPU / GFX ISA

Sources