s_gl1_inv GPU Native ISA AMD Scalar

Scalar Memory

s_gl1_inv

Invalidate the GL1 cache only.

Encoding

Binary Layout (AMD RDNA 3.5)
SOFFSET
63:57
unassigned
56:53
OFFSET
52:32
111101
31:26
00100000
25:18
unassigned
17:15
GLC
14
DLC
13
SDATA
12:6
SBASE
5:0
 

The ENC_SMEM layout from AMD's machine-readable ISA specification (AMD RDNA 3.5). Opcode 32 in OP rebuilds 0x00000000F4800000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD RDNA 2 (opcode 31, field layout), AMD RDNA 1 (opcode 31, field layout). The same in AMD RDNA 3.

Format SMEM
Width 64 bits
Opcode 32
Identifier 0x00000000F4800000

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Memory

Reference

AMDGPU / GFX ISA

Sources