Uniform (Read-Only) Load Memory
Load a value from memory that is known to be identical across all threads/lanes in the group, via the scalar/uniform data path.
Vendor-Neutral Definition
d = *addr, issued once per wavefront/warp on the scalar path rather than once per lane on the vector path, since the loaded value is guaranteed uniform.
⚠️ Cross-vendor mappings describe semantic relationships and are not guaranteed one-to-one compiler
translations.
equivalent with restrictions
Both load a value known to be uniform across the thread group through a dedicated scalar/read-only data path rather than the general per-lane path.
| Property | NVIDIA PTX | AMDGPU |
|---|---|---|
| Instruction | ldu | s_load_dword |
| ISA Layer | Virtual | Native |
| Data Types | - | - |
| Version / Target Introduced | PTX ISA 2.0 | gfx942/gfx1100 |
Important Differences
- PTX's ldu is a per-thread instruction carrying an explicit compiler promise that the loaded value happens to be uniform; AMDGPU's s_load_dword is inherently scalar (issued once per wavefront, result placed in an SGPR shared by all lanes) - the uniformity is architectural on AMDGPU rather than an optional hint on an otherwise-per-lane instruction.
Source Evidence
- Parallel Thread Execution ISA ↗ - NVIDIA Corporation
- "AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗ - Advanced Micro Devices, Inc.
Verification method: documentation