AMDGPU / GFX Instructions GPU Native ISA AMD
1960 instructions - showing 100 per page, page 10 of 20 - AMDGPU/GFX is AMD's native, low-level
GPU instruction set family, assembled directly with no virtual intermediate layer. Supported
instructions and their exact encodings vary by GFX compatibility target (e.g.
gfx942, gfx1100). Scalar instructions execute once per wavefront on
the Scalar ALU; vector instructions execute per-lane on the Vector ALU, gated by the EXEC mask.
| Mnemonic | Syntax | Format | GFX Targets | Unit | Summary |
|---|---|---|---|---|---|
| scratch_load_lds_sbyte | scratch_load_lds_sbyte | SCRATCH | Load 8 bits of untyped data from the scratch aperture, sign extend to 32 bits and store the result into a data share. | ||
| scratch_load_lds_sshort | scratch_load_lds_sshort | SCRATCH | Load 16 bits of untyped data from the scratch aperture, sign extend to 32 bits and store the result into a data share. | ||
| scratch_load_lds_ubyte | scratch_load_lds_ubyte | SCRATCH | Load 8 bits of untyped data from the scratch aperture, zero extend to 32 bits and store the result into a data share. | ||
| scratch_load_lds_ushort | scratch_load_lds_ushort | SCRATCH | Load 16 bits of untyped data from the scratch aperture, zero extend to 32 bits and store the result into a data share. | ||
| scratch_load_sbyte | scratch_load_sbyte | SCRATCH | Load 8 bits of signed data from the scratch aperture, sign extend to 32 bits and store the result into a vector register. | ||
| scratch_load_sbyte_d16 | scratch_load_sbyte_d16 | SCRATCH | Load 8 bits of signed data from the scratch aperture, sign extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register. | ||
| scratch_load_sbyte_d16_hi | scratch_load_sbyte_d16_hi | SCRATCH | Load 8 bits of signed data from the scratch aperture, sign extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register. | ||
| scratch_load_short_d16 | scratch_load_short_d16 | SCRATCH | Load 16 bits of unsigned data from the scratch aperture and store the result into the low 16 bits of a 32-bit vector register. | ||
| scratch_load_short_d16_hi | scratch_load_short_d16_hi | SCRATCH | Load 16 bits of unsigned data from the scratch aperture and store the result into the high 16 bits of a 32-bit vector register. | ||
| scratch_load_sshort | scratch_load_sshort | SCRATCH | Load 16 bits of signed data from the scratch aperture, sign extend to 32 bits and store the result into a vector register. | ||
| scratch_load_ubyte | scratch_load_ubyte | SCRATCH | Load 8 bits of unsigned data from the scratch aperture, zero extend to 32 bits and store the result into a vector register. | ||
| scratch_load_ubyte_d16 | scratch_load_ubyte_d16 | SCRATCH | Load 8 bits of unsigned data from the scratch aperture, zero extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register. | ||
| scratch_load_ubyte_d16_hi | scratch_load_ubyte_d16_hi | SCRATCH | Load 8 bits of unsigned data from the scratch aperture, zero extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register. | ||
| scratch_load_ushort | scratch_load_ushort | SCRATCH | Load 16 bits of unsigned data from the scratch aperture, zero extend to 32 bits and store the result into a vector register. | ||
| scratch_store_block | scratch_store_block | SCRATCH | Store a block of data to the scratch aperture. | ||
| scratch_store_byte | scratch_store_byte | SCRATCH | Store 8 bits of data from a vector register into the scratch aperture. | ||
| scratch_store_byte_d16_hi | scratch_store_byte_d16_hi | SCRATCH | Store 8 bits of data from the high 16 bits of a 32-bit vector register into the scratch aperture. | ||
| scratch_store_dword | scratch_store_dword | SCRATCH | Store 32 bits of data from vector input registers into the scratch aperture. | ||
| scratch_store_dwordx2 | scratch_store_dwordx2 | SCRATCH | Store 64 bits of data from vector input registers into the scratch aperture. | ||
| scratch_store_dwordx3 | scratch_store_dwordx3 | SCRATCH | Store 96 bits of data from vector input registers into the scratch aperture. | ||
| scratch_store_dwordx4 | scratch_store_dwordx4 | SCRATCH | Store 128 bits of data from vector input registers into the scratch aperture. | ||
| scratch_store_short | scratch_store_short | SCRATCH | Store 16 bits of data from a vector register into the scratch aperture. | ||
| scratch_store_short_d16_hi | scratch_store_short_d16_hi | SCRATCH | Store 16 bits of data from the high 16 bits of a 32-bit vector register into the scratch aperture. | ||
| tbuffer_load_d16_format_x | tbuffer_load_d16_format_x | MTBUF | gfx1100 | Load 1-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result… | |
| tbuffer_load_d16_format_xy | tbuffer_load_d16_format_xy | MTBUF | gfx1100 | Load 2-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result… | |
| tbuffer_load_d16_format_xyz | tbuffer_load_d16_format_xyz | MTBUF | gfx1100 | Load 3-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result… | |
| tbuffer_load_d16_format_xyzw | tbuffer_load_d16_format_xyzw | MTBUF | gfx1100 | Load 4-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result… | |
| tbuffer_load_format_d16_x | tbuffer_load_format_d16_x | MTBUF | Load 1-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result… | ||
| tbuffer_load_format_d16_xy | tbuffer_load_format_d16_xy | MTBUF | Load 2-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result… | ||
| tbuffer_load_format_d16_xyz | tbuffer_load_format_d16_xyz | MTBUF | Load 3-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result… | ||
| tbuffer_load_format_d16_xyzw | tbuffer_load_format_d16_xyzw | MTBUF | Load 4-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result… | ||
| tbuffer_load_format_x | tbuffer_load_format_x | MTBUF | gfx1100 | Load 1-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a… | |
| tbuffer_load_format_xy | tbuffer_load_format_xy | MTBUF | gfx1100 | Load 2-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a… | |
| tbuffer_load_format_xyz | tbuffer_load_format_xyz | MTBUF | gfx1100 | Load 3-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a… | |
| tbuffer_load_format_xyzw | tbuffer_load_format_xyzw | MTBUF | gfx1100 | Load 4-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a… | |
| tbuffer_store_d16_format_x | tbuffer_store_d16_format_x | MTBUF | gfx1100 | Convert 16 bits of data from vector input registers into 1-component formatted data and store the data into a buffer surface. | |
| tbuffer_store_d16_format_xy | tbuffer_store_d16_format_xy | MTBUF | gfx1100 | Convert 32 bits of data from vector input registers into 2-component formatted data and store the data into a buffer surface. | |
| tbuffer_store_d16_format_xyz | tbuffer_store_d16_format_xyz | MTBUF | gfx1100 | Convert 48 bits of data from vector input registers into 3-component formatted data and store the data into a buffer surface. | |
| tbuffer_store_d16_format_xyzw | tbuffer_store_d16_format_xyzw | MTBUF | gfx1100 | Convert 64 bits of data from vector input registers into 4-component formatted data and store the data into a buffer surface. | |
| tbuffer_store_format_d16_x | tbuffer_store_format_d16_x | MTBUF | Convert 16 bits of data from vector input registers into 1-component formatted data and store the data into a buffer surface. | ||
| tbuffer_store_format_d16_xy | tbuffer_store_format_d16_xy | MTBUF | Convert 32 bits of data from vector input registers into 2-component formatted data and store the data into a buffer surface. | ||
| tbuffer_store_format_d16_xyz | tbuffer_store_format_d16_xyz | MTBUF | Convert 48 bits of data from vector input registers into 3-component formatted data and store the data into a buffer surface. | ||
| tbuffer_store_format_d16_xyzw | tbuffer_store_format_d16_xyzw | MTBUF | Convert 64 bits of data from vector input registers into 4-component formatted data and store the data into a buffer surface. | ||
| tbuffer_store_format_x | tbuffer_store_format_x | MTBUF | gfx1100 | Convert 32 bits of data from vector input registers into 1-component formatted data and store the data into a buffer surface. | |
| tbuffer_store_format_xy | tbuffer_store_format_xy | MTBUF | gfx1100 | Convert 64 bits of data from vector input registers into 2-component formatted data and store the data into a buffer surface. | |
| tbuffer_store_format_xyz | tbuffer_store_format_xyz | MTBUF | gfx1100 | Convert 96 bits of data from vector input registers into 3-component formatted data and store the data into a buffer surface. | |
| tbuffer_store_format_xyzw | tbuffer_store_format_xyzw | MTBUF | gfx1100 | Convert 128 bits of data from vector input registers into 4-component formatted data and store the data into a buffer surface. | |
| tensor_save | tensor_save | FLAT | AMDGPU FLAT vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| tensor_stop | tensor_stop | FLAT | AMDGPU FLAT vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_accvgpr_mov_b32 | v_accvgpr_mov_b32 | VOP1 | Move data from one accumulator register to another accumulator register. | ||
| v_accvgpr_read_b32 | v_accvgpr_read_b32 | VOP3 | AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_accvgpr_write_b32 | v_accvgpr_write_b32 | VOP3 | AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_add3_u32 | v_add3_u32 | VOP3 | gfx1100 | Add three unsigned inputs and store the result into a vector register. No carry-in or carry-out support. | |
| v_add_co_u32 | v_add_co_u32 | VOP2 | gfx1100 | Add two unsigned 32-bit integer inputs, store the result into a vector register and store the carry-out mask into a scalar register. | |
| v_add_f16 | v_add_f16 | VOP2 | gfx1100 | Add two floating point inputs and store the result into a vector register. | |
| v_add_f32 | v_add_f32 VDST, S0, S1 | VOP2 | gfx942, gfx1100 | Vector ALU | Per-lane single-precision floating-point add. |
| v_add_f64 | v_add_f64 | VOP2 | gfx1100 | Add two floating point inputs and store the result into a vector register. | |
| v_add_f64_pseudo | v_add_f64_pseudo | VOP2 | AMDGPU VOP2 vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_add_i16 | v_add_i16 | VOP3 | Add two signed 16-bit integer inputs and store the result into a vector register. No carry-in or carry-out support. | ||
| v_add_i32 | v_add_i32 | VOP2 | Add two signed 32-bit integer inputs and store the result into a vector register. No carry-in or carry-out support. | ||
| v_add_lshl_u32 | v_add_lshl_u32 | VOP3 | gfx1100 | Add the first two integer inputs, then given a shift count in the third input, calculate the logical shift left of the intermediate result, then… | |
| v_add_max_i32 | v_add_max_i32 | VOP3 | AMDGPU VOP3 vector instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_add_max_u32 | v_add_max_u32 | VOP3 | AMDGPU VOP3 vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_add_min_i32 | v_add_min_i32 | VOP3 | AMDGPU VOP3 vector instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_add_min_u32 | v_add_min_u32 | VOP3 | AMDGPU VOP3 vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_add_nc_i16 | v_add_nc_i16 | VOP3 | gfx1100 | Add two signed 16-bit integer inputs and store the result into a vector register. No carry-in or carry-out support. | |
| v_add_nc_i32 | v_add_nc_i32 | VOP3 | gfx1100 | Add two signed 32-bit integer inputs and store the result into a vector register. No carry-in or carry-out support. | |
| v_add_nc_u16 | v_add_nc_u16 | VOP3 | gfx1100 | Add two unsigned 16-bit integer inputs and store the result into a vector register. No carry-in or carry-out support. | |
| v_add_nc_u64 | v_add_nc_u64 | VOP2 | AMDGPU VOP2 vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_add_u16 | v_add_u16 | VOP2 | Add two unsigned 16-bit integer inputs and store the result into a vector register. No carry-in or carry-out support. | ||
| v_add_u32 | v_add_u32 VDST, S0, S1 | VOP2 | gfx942, gfx1100 | Vector ALU | Per-lane add of two 32-bit unsigned vector operands. |
| v_addc_co_u32 | v_addc_co_u32 | VOP2 | Add two unsigned 32-bit integer inputs and a bit from a carry-in mask, store the result into a vector register and store the carry-out mask into a… | ||
| v_addc_u32 | v_addc_u32 | VOP2 | AMDGPU VOP2 vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_alignbit_b32 | v_alignbit_b32 | VOP3 | gfx1100 | Align a 64-bit value encoded in the first two inputs to a bit position specified in the third input, then store the result into a 32-bit vector… | |
| v_alignbit_b32_opsel | v_alignbit_b32_opsel | VOP3 | AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_alignbyte_b32 | v_alignbyte_b32 | VOP3 | gfx1100 | Align a 64-bit value encoded in the first two inputs to a byte position specified in the third input, then store the result into a 32-bit vector… | |
| v_alignbyte_b32_fake16 | v_alignbyte_b32_fake16 | VOP3 | AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_alignbyte_b32_opsel | v_alignbyte_b32_opsel | VOP3 | AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_alignbyte_b32_t16 | v_alignbyte_b32_t16 | VOP3 | AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_and_b16 | v_and_b16 | VOP3 | gfx1100 | Calculate bitwise AND on two vector inputs and store the result into a vector register. | |
| v_and_b16_fake16 | v_and_b16_fake16 | VOP2 | AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_and_b16_t16 | v_and_b16_t16 | VOP2 | AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_and_b32 | v_and_b32 | VOP2 | gfx1100 | Calculate bitwise AND on two vector inputs and store the result into a vector register. | |
| v_and_or_b32 | v_and_or_b32 | VOP3 | gfx1100 | Calculate bitwise AND on the first two vector inputs, then compute the bitwise OR of the intermediate result and the third vector input, then store… | |
| v_ashr_i32 | v_ashr_i32 | VOP2 | AMDGPU VOP2 vector instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_ashr_i64 | v_ashr_i64 | VOP3 | AMDGPU VOP3 vector instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_ashr_pk_i8_i32 | v_ashr_pk_i8_i32 | VOP3 | Given two signed 32-bit integers and a shift count, calculate the arithmetic shift right (preserving sign bit) of the two integers, saturate the two… | ||
| v_ashr_pk_u8_i32 | v_ashr_pk_u8_i32 | VOP3 | Given two signed 32-bit integers and a shift count, calculate the arithmetic shift right (preserving sign bit) of the two integers, saturate the two… | ||
| v_ashrrev_i16 | v_ashrrev_i16 | VOP2 | gfx1100 | Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the… | |
| v_ashrrev_i32 | v_ashrrev_i32 | VOP2 | gfx1100 | Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the… | |
| v_ashrrev_i64 | v_ashrrev_i64 | VOP3 | gfx1100 | Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the… | |
| v_bcnt_u32_b32 | v_bcnt_u32_b32 VDST, S0, S1 | VOP3 | gfx942, gfx1100 | Vector ALU | Per-lane accumulating population count. |
| v_bfe_i32 | v_bfe_i32 | VOP3 | gfx1100 | Extract a signed bitfield from the first input using field offset from the second input and size from the third input, then store the result into a… | |
| v_bfe_u32 | v_bfe_u32 | VOP3 | gfx1100 | Extract an unsigned bitfield from the first input using field offset from the second input and size from the third input, then store the result into… | |
| v_bfi_b32 | v_bfi_b32 | VOP3 | gfx1100 | Overwrite a bitfield in the third input with a bitfield from the second input using a mask from the first input, then store the result into a vector… | |
| v_bfm_b32 | v_bfm_b32 | VOP2 | gfx1100 | Calculate a bitfield mask given a field offset and size and store the result into a vector register. | |
| v_bfrev_b32 | v_bfrev_b32 | VOP1 | gfx1100 | Reverse the order of bits in a vector input and store the result into a vector register. | |
| v_bitop3_b16 | v_bitop3_b16 | VOP3 | Calculate the generic bitwise operation of three 16-bit vector inputs using a truth table encoded in the instruction and store the result into a… | ||
| v_bitop3_b16_gfx1250 | v_bitop3_b16_gfx1250 | VOP3 | AMDGPU VOP3 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_bitop3_b32 | v_bitop3_b32 | VOP3 | Calculate the generic bitwise operation of three 32-bit vector inputs using a truth table encoded in the instruction and store the result into a… |
Source
Normalized from AMD's official ROCm documentation, with the LLVM AMDGPU backend documentation as supplementary compiler-target information. ROCm documentation ↗