AMDGPU / GFX Instructions GPU Native ISA AMD
1960 instructions - showing 100 per page, page 8 of 20 - AMDGPU/GFX is AMD's native, low-level
GPU instruction set family, assembled directly with no virtual intermediate layer. Supported
instructions and their exact encodings vary by GFX compatibility target (e.g.
gfx942, gfx1100). Scalar instructions execute once per wavefront on
the Scalar ALU; vector instructions execute per-lane on the Vector ALU, gated by the EXEC mask.
| Mnemonic | Syntax | Format | GFX Targets | Unit | Summary |
|---|---|---|---|---|---|
| s_cmpk_ge_u32 | s_cmpk_ge_u32 | SOPK | gfx1100 | Set SCC to 1 iff scalar input is greater than or equal to the zero extension of a literal 16-bit constant. | |
| s_cmpk_gt_i32 | s_cmpk_gt_i32 | SOPK | gfx1100 | Set SCC to 1 iff scalar input is greater than the sign extension of a literal 16-bit constant. | |
| s_cmpk_gt_u32 | s_cmpk_gt_u32 | SOPK | gfx1100 | Set SCC to 1 iff scalar input is greater than the zero extension of a literal 16-bit constant. | |
| s_cmpk_le_i32 | s_cmpk_le_i32 | SOPK | gfx1100 | Set SCC to 1 iff scalar input is less than or equal to the sign extension of a literal 16-bit constant. | |
| s_cmpk_le_u32 | s_cmpk_le_u32 | SOPK | gfx1100 | Set SCC to 1 iff scalar input is less than or equal to the zero extension of a literal 16-bit constant. | |
| s_cmpk_lg_i32 | s_cmpk_lg_i32 | SOPK | gfx1100 | Set SCC to 1 iff scalar input is less than or greater than the sign extension of a literal 16-bit constant. | |
| s_cmpk_lg_u32 | s_cmpk_lg_u32 | SOPK | gfx1100 | Set SCC to 1 iff scalar input is less than or greater than the zero extension of a literal 16-bit constant. | |
| s_cmpk_lt_i32 | s_cmpk_lt_i32 | SOPK | gfx1100 | Set SCC to 1 iff scalar input is less than the sign extension of a literal 16-bit constant. | |
| s_cmpk_lt_u32 | s_cmpk_lt_u32 | SOPK | gfx1100 | Set SCC to 1 iff scalar input is less than the zero extension of a literal 16-bit constant. | |
| s_cselect_b32 | s_cselect_b32 | SOP2 | gfx1100 | Select the first input if SCC is true otherwise select the second input, then store the selected input into a scalar register. | |
| s_cselect_b64 | s_cselect_b64 | SOP2 | gfx1100 | Select the first input if SCC is true otherwise select the second input, then store the selected input into a scalar register. | |
| s_ctz_i32_b32 | s_ctz_i32_b32 | SOP1 | gfx1100 | Count the number of trailing "0" bits before the first "1" in a scalar input and store the result into a scalar register. | |
| s_ctz_i32_b64 | s_ctz_i32_b64 | SOP1 | gfx1100 | Count the number of trailing "0" bits before the first "1" in a scalar input and store the result into a scalar register. | |
| s_cvt_f16_f32 | s_cvt_f16_f32 | SOP1 | gfx1100 | Convert from a single-precision float input to a half-precision float value and store the result into a scalar register. | |
| s_cvt_f32_f16 | s_cvt_f32_f16 | SOP1 | gfx1100 | Convert from a half-precision float input to a single-precision float value and store the result into a scalar register. | |
| s_cvt_f32_i32 | s_cvt_f32_i32 | SOP1 | gfx1100 | Convert from a signed 32-bit integer input to a single-precision float value and store the result into a scalar register. | |
| s_cvt_f32_u32 | s_cvt_f32_u32 | SOP1 | gfx1100 | Convert from an unsigned 32-bit integer input to a single-precision float value and store the result into a scalar register. | |
| s_cvt_hi_f32_f16 | s_cvt_hi_f32_f16 | SOP1 | gfx1100 | Convert from a half-precision float value in the high 16 bits of a scalar input to a single-precision float value and store the result into a scalar… | |
| s_cvt_i32_f32 | s_cvt_i32_f32 | SOP1 | gfx1100 | Convert from a single-precision float input to a signed 32-bit integer value and store the result into a scalar register. | |
| s_cvt_pk_rtz_f16_f32 | s_cvt_pk_rtz_f16_f32 | SOP2 | gfx1100 | Convert two single-precision float inputs into a packed half-precision float result using round toward zero semantics (ignore the current rounding… | |
| s_cvt_u32_f32 | s_cvt_u32_f32 | SOP1 | gfx1100 | Convert from a single-precision float input to an unsigned 32-bit integer value and store the result into a scalar register. | |
| s_dcache_inv | s_dcache_inv | SMEM | Invalidate the scalar (L0) data cache. | ||
| s_dcache_inv_vol | s_dcache_inv_vol | SMEM | Invalidate the scalar (L0) data cache volatile lines. | ||
| s_dcache_wb | s_dcache_wb | SMEM | Write back dirty data in the scalar (L0) data cache. | ||
| s_dcache_wb_vol | s_dcache_wb_vol | SMEM | Write back dirty data in the scalar (L0) data cache volatile lines. | ||
| s_decperflevel | s_decperflevel | SOPP | gfx1100 | Decrement performance counter specified in SIMM16[3:0] by 1. | |
| s_delay_alu | s_delay_alu | SOPP | gfx1100 | Insert delay between dependent SALU/VALU instructions. | |
| s_endpgm | s_endpgm | SOPP | gfx1100 | End of program; terminate wavefront. | |
| s_endpgm_saved | s_endpgm_saved | SOPP | gfx1100 | End of program; signal that a wave has been saved by the context-switch trap handler and terminate wavefront. | |
| s_ff0_i32_b32 | s_ff0_i32_b32 | SOP1 | Count the number of trailing "1" bits before the first "0" in a scalar input and store the result into a scalar register. | ||
| s_ff0_i32_b64 | s_ff0_i32_b64 | SOP1 | Count the number of trailing "1" bits before the first "0" in a scalar input and store the result into a scalar register. | ||
| s_ff1_i32_b32 | s_ff1_i32_b32 | SOP1 | gfx1100 | Count the number of trailing "0" bits before the first "1" in a scalar input and store the result into a scalar register. | |
| s_ff1_i32_b64 | s_ff1_i32_b64 | SOP1 | gfx1100 | Count the number of trailing "0" bits before the first "1" in a scalar input and store the result into a scalar register. | |
| s_flbit_i32 | s_flbit_i32 | SOP1 | gfx1100 | Count the number of leading bits that are the same as the sign bit of a scalar input and store the result into a scalar register. | |
| s_flbit_i32_b32 | s_flbit_i32_b32 | SOP1 | gfx1100 | Count the number of leading "0" bits before the first "1" in a scalar input and store the result into a scalar register. | |
| s_flbit_i32_b64 | s_flbit_i32_b64 | SOP1 | gfx1100 | Count the number of leading "0" bits before the first "1" in a scalar input and store the result into a scalar register. | |
| s_flbit_i32_i64 | s_flbit_i32_i64 | SOP1 | gfx1100 | Count the number of leading bits that are the same as the sign bit of a scalar input and store the result into a scalar register. | |
| s_floor_f16 | s_floor_f16 | SOP1 | gfx1100 | Round the half-precision float input down to previous integer and store the result in floating point format into a scalar register. | |
| s_floor_f32 | s_floor_f32 | SOP1 | gfx1100 | Round the single-precision float input down to previous integer and store the result in floating point format into a scalar register. | |
| s_get_barrier_state | s_get_barrier_state | SOP1 | AMDGPU SOP1 scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| s_get_pc_i64 | s_get_pc_i64 | SOP1 | gfx1100 | AMDGPU SOP1 scalar instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | |
| s_get_shader_cycles_u64 | s_get_shader_cycles_u64 | SOP1 | AMDGPU SOP1 scalar instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| s_get_waveid_in_workgroup | s_get_waveid_in_workgroup | SMEM | Return the wave's ID within a workgroup 0-(N-1). | ||
| s_getpc_b64 | s_getpc_b64 | SOP1 | gfx1100 | Store the address of the next instruction to a scalar register. | |
| s_gl1_inv | s_gl1_inv | SMEM | Invalidate the GL1 cache only. | ||
| s_icache_inv | s_icache_inv | SOPP | gfx1100 | Invalidate entire first level instruction cache. | |
| s_incperflevel | s_incperflevel | SOPP | gfx1100 | Increment performance counter specified in SIMM16[3:0] by 1. | |
| s_load_dword | s_load_dword SDST, SBASE, offset | SMEM | gfx942, gfx1100 | Scalar Memory Unit | Load one 32-bit dword from memory into a scalar register, wavefront-uniform. |
| s_lshl1_add_u32 | s_lshl1_add_u32 | SOP2 | gfx1100 | Calculate the logical shift left of the first input by 1, then add the second input, store the result into a scalar register and set SCC iff the… | |
| s_lshl2_add_u32 | s_lshl2_add_u32 | SOP2 | gfx1100 | Calculate the logical shift left of the first input by 2, then add the second input, store the result into a scalar register and set SCC iff the… | |
| s_lshl3_add_u32 | s_lshl3_add_u32 | SOP2 | gfx1100 | Calculate the logical shift left of the first input by 3, then add the second input, store the result into a scalar register and set SCC iff the… | |
| s_lshl4_add_u32 | s_lshl4_add_u32 | SOP2 | gfx1100 | Calculate the logical shift left of the first input by 4, then add the second input, store the result into a scalar register and set SCC iff the… | |
| s_lshl_b32 | s_lshl_b32 | SOP2 | gfx1100 | Given a shift count in the second scalar input, calculate the logical shift left of the first scalar input, store the result into a scalar register… | |
| s_lshl_b64 | s_lshl_b64 | SOP2 | gfx1100 | Given a shift count in the second scalar input, calculate the logical shift left of the first scalar input, store the result into a scalar register… | |
| s_lshr_b32 | s_lshr_b32 | SOP2 | gfx1100 | Given a shift count in the second scalar input, calculate the logical shift right of the first scalar input, store the result into a scalar register… | |
| s_lshr_b64 | s_lshr_b64 | SOP2 | gfx1100 | Given a shift count in the second scalar input, calculate the logical shift right of the first scalar input, store the result into a scalar register… | |
| s_max_f16 | s_max_f16 | SOP2 | gfx1100 | Select the maximum of two half-precision float inputs and store the selected value into a scalar register. | |
| s_max_f32 | s_max_f32 | SOP2 | gfx1100 | Select the maximum of two single-precision float inputs and store the selected value into a scalar register. | |
| s_max_i32 | s_max_i32 | SOP2 | gfx1100 | Select the maximum of two signed 32-bit integer inputs, store the selected value into a scalar register and set SCC iff the first value is selected. | |
| s_max_num_f16 | s_max_num_f16 | SOP2 | gfx1100 | Select the IEEE maximumNumber() of two half-precision float inputs and store the selected value into a scalar register. | |
| s_max_num_f32 | s_max_num_f32 | SOP2 | gfx1100 | Select the IEEE maximumNumber() of two single-precision float inputs and store the selected value into a scalar register. | |
| s_max_u32 | s_max_u32 | SOP2 | gfx1100 | Select the maximum of two unsigned 32-bit integer inputs, store the selected value into a scalar register and set SCC iff the first value is selected. | |
| s_maximum_f16 | s_maximum_f16 | SOP2 | Select the IEEE maximum() of two half-precision float inputs and store the selected value into a scalar register. | ||
| s_maximum_f32 | s_maximum_f32 | SOP2 | Select the IEEE maximum() of two single-precision float inputs and store the selected value into a scalar register. | ||
| s_memrealtime | s_memrealtime | SMEM | Return current 64-bit RTC. | ||
| s_memtime | s_memtime | SMEM | Return current 64-bit timestamp. | ||
| s_min_f16 | s_min_f16 | SOP2 | gfx1100 | Select the minimum of two half-precision float inputs and store the selected value into a scalar register. | |
| s_min_f32 | s_min_f32 | SOP2 | gfx1100 | Select the minimum of two single-precision float inputs and store the selected value into a scalar register. | |
| s_min_i32 | s_min_i32 | SOP2 | gfx1100 | Select the minimum of two signed 32-bit integer inputs, store the selected value into a scalar register and set SCC iff the first value is selected. | |
| s_min_num_f16 | s_min_num_f16 | SOP2 | gfx1100 | Select the IEEE minimumNumber() of two half-precision float inputs and store the selected value into a scalar register. | |
| s_min_num_f32 | s_min_num_f32 | SOP2 | gfx1100 | Select the IEEE minimumNumber() of two single-precision float inputs and store the selected value into a scalar register. | |
| s_min_u32 | s_min_u32 | SOP2 | gfx1100 | Select the minimum of two unsigned 32-bit integer inputs, store the selected value into a scalar register and set SCC iff the first value is selected. | |
| s_minimum_f16 | s_minimum_f16 | SOP2 | Select the IEEE minimum() of two half-precision float inputs and store the selected value into a scalar register. | ||
| s_minimum_f32 | s_minimum_f32 | SOP2 | Select the IEEE minimum() of two single-precision float inputs and store the selected value into a scalar register. | ||
| s_monitor_sleep | s_monitor_sleep | SOPP | AMDGPU SOPP scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| s_mov_b32 | s_mov_b32 | SOP1 | gfx1100 | Move scalar input into a scalar register. | |
| s_mov_b64 | s_mov_b64 | SOP1 | gfx1100 | Move scalar input into a scalar register. | |
| s_movk_i32 | s_movk_i32 | SOPK | gfx1100 | Sign extend a literal 16-bit constant and store the result into a scalar register. | |
| s_movreld_b32 | s_movreld_b32 | SOP1 | gfx1100 | Move data from a scalar input into a relatively-indexed scalar register. | |
| s_movreld_b64 | s_movreld_b64 | SOP1 | gfx1100 | Move data from a scalar input into a relatively-indexed scalar register. | |
| s_movrels_b32 | s_movrels_b32 | SOP1 | gfx1100 | Move data from a relatively-indexed scalar register into another scalar register. | |
| s_movrels_b64 | s_movrels_b64 | SOP1 | gfx1100 | Move data from a relatively-indexed scalar register into another scalar register. | |
| s_movrelsd_2_b32 | s_movrelsd_2_b32 | SOP1 | gfx1100 | Move data from a relatively-indexed scalar register into another relatively-indexed scalar register, using different offsets for each index. | |
| s_mul_f16 | s_mul_f16 | SOP2 | gfx1100 | Multiply two floating point inputs and store the result into a scalar register. | |
| s_mul_f32 | s_mul_f32 | SOP2 | gfx1100 | Multiply two floating point inputs and store the result into a scalar register. | |
| s_mul_hi_i32 | s_mul_hi_i32 | SOP2 | gfx1100 | Multiply two signed integers and store the high 32 bits of the result into a scalar register. | |
| s_mul_hi_u32 | s_mul_hi_u32 | SOP2 | gfx1100 | Multiply two unsigned integers and store the high 32 bits of the result into a scalar register. | |
| s_mul_i32 | s_mul_i32 SDST, S0, S1 | SOP2 | gfx942, gfx1100 | Scalar ALU | Multiply two 32-bit signed scalar operands, wavefront-uniform, low 32 bits of the product. |
| s_mul_u64 | s_mul_u64 | SOP2 | Multiply two unsigned 64-bit integer inputs and store the result into a scalar register. | ||
| s_mulk_i32 | s_mulk_i32 | SOPK | gfx1100 | Multiply a scalar input with the sign extension of a literal 16-bit constant and store the result into a scalar register. | |
| s_nand_b32 | s_nand_b32 | SOP2 | gfx1100 | Calculate bitwise NAND on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero. | |
| s_nand_b64 | s_nand_b64 | SOP2 | gfx1100 | Calculate bitwise NAND on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero. | |
| s_nand_saveexec_b32 | s_nand_saveexec_b32 | SOP1 | gfx1100 | Calculate bitwise NAND on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is… | |
| s_nand_saveexec_b64 | s_nand_saveexec_b64 | SOP1 | gfx1100 | Calculate bitwise NAND on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is… | |
| s_nop | s_nop | SOPP | gfx1100 | Do nothing. | |
| s_nor_b32 | s_nor_b32 | SOP2 | gfx1100 | Calculate bitwise NOR on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero. | |
| s_nor_b64 | s_nor_b64 | SOP2 | gfx1100 | Calculate bitwise NOR on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero. | |
| s_nor_saveexec_b32 | s_nor_saveexec_b32 | SOP1 | gfx1100 | Calculate bitwise NOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is… | |
| s_nor_saveexec_b64 | s_nor_saveexec_b64 | SOP1 | gfx1100 | Calculate bitwise NOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is… | |
| s_not_b32 | s_not_b32 | SOP1 | gfx1100 | Calculate bitwise negation on a scalar input, store the result into a scalar register and set SCC iff the result is nonzero. |
Source
Normalized from AMD's official ROCm documentation, with the LLVM AMDGPU backend documentation as supplementary compiler-target information. ROCm documentation ↗