image_store_mip_pck GPU Native ISA AMD Vector

IMAGE STORE MIP PCK Image / Texture Memory

image_store_mip_pck

Store a texel from a vector register to a user-specified miplevel in an image surface.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (MIMG) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format MIMG
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Image / Texture Memory

Reference

AMDGPU / GFX ISA

Description

Store a texel from a vector register to a user-specified miplevel in an image surface. The texel data is already packed and the format specified in the resource descriptor is ignored.

Example

image_store_mip_pck v[1:2], v[2:3], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources