image_store_mip_pck2 GPU Native ISA AMD Vector

Image / Texture Memory

image_store_mip_pck2

Store 2 horizontal elements from a vector register to a user-specified miplevel in an image surface.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (MIMG) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format MIMG

Operands

  • VDATA
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • VADDR
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • SRSRC
    Read. N/A Data format: 256-bit image resource constant. (OPR_SREG_NONULL, FMT_IMG)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_MIMG encoding (AMD RDNA 2).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Image / Texture Memory

Reference

AMDGPU / GFX ISA

Description

Store 2 horizontal elements from a vector register to a user-specified miplevel in an image surface. The texel data is already packed and the format specified in the resource descriptor is ignored. Illegal for element sizes greater than 64 bits.

Sources