image_store_pck GPU Native ISA AMD Vector

Image / Texture Memory

image_store_pck

Store a texel from a vector register to the largest miplevel in an image surface.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (MIMG) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format MIMG

Operands

  • VDATA
    Read. N/A Data format: Value can be anything. (OPR_VGPR_OR_ACCVGPR, FMT_ANY)
  • VADDR
    Read. N/A Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • SRSRC
    Read. N/A Data format: 256-bit image resource constant. (OPR_SREG, FMT_IMG)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_MIMG encoding (AMD CDNA 2).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Image / Texture Memory

Reference

AMDGPU / GFX ISA

Description

Store a texel from a vector register to the largest miplevel in an image surface. The texel data is already packed and the format specified in the resource descriptor is ignored.

Example

image_store_pck v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources