tensor_store_from_lds GPU Native ISA AMD Vector

Image / Texture Memory

tensor_store_from_lds

DMA instruction to store tensor data to Global from LDS.

Encoding

Binary Layout (AMD CDNA 5)
VADDR3
95:88
VADDR2
87:80
VADDR1
79:72
VADDR0
71:64
VADDR4
63:56
TFE
55
TH
54:52
SCOPE
51:50
RSRC
49:41
unassigned
40
VDATA
39:32
110100
31:26
DMASK
25:22
11000101
21:14
unassigned
13:8
NV
7
A16
6
D16
5
R128
4
unassigned
3
DIM
2:0
 

The ENC_VIMAGE layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 197 in OP rebuilds 0x0000000000000000D0314000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. No other generation in the specification defines this instruction.

Format MIMG
Width 96 bits
Opcode 197
Identifier 0x0000000000000000D0314000

Operands

  • VADDR0
    Read. Numbered scalar GPR. Does not include specially-named SGPR operands. Data format: Value can be anything. (OPR_SGPR, FMT_ANY)
  • VADDR1
    Read. Numbered scalar GPR. Does not include specially-named SGPR operands. Data format: Value can be anything. (OPR_SGPR, FMT_ANY)
  • VADDR2
    Read. Any scalar GPR operand including VCC and NULL. Data format: Value can be anything. (OPR_SREG, FMT_ANY)
  • VADDR3
    Read. Any scalar GPR operand including VCC and NULL. Data format: Value can be anything. (OPR_SREG, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VIMAGE encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Image / Texture Memory

Reference

AMDGPU / GFX ISA

Sources