image_sample_c_d_o_g16 GPU Native ISA AMD Vector

Image / Texture Memory

image_sample_c_d_o_g16

Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers.

Encoding

Binary Layout (AMD RDNA 4)
VADDR3
95:88
VADDR2
87:80
VADDR1
79:72
VADDR0
71:64
SAMP
63:55
TH
54:52
SCOPE
51:50
RSRC
49:41
LWE
40
VDATA
39:32
111001
31:26
DMASK
25:22
00111100
21:14
UNORM
13
unassigned
12:8
NV
7
A16
6
D16
5
R128
4
TFE
3
DIM
2:0
 

The ENC_VSAMPLE layout from AMD's machine-readable ISA specification (AMD RDNA 4). Opcode 60 in OP rebuilds 0x0000000000000000E40F0000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD RDNA 3.5 (encoding ENC_MIMG, field layout), AMD RDNA 3 (encoding ENC_MIMG, field layout), AMD RDNA 2 (layout not verifiable), AMD RDNA 1 (layout not verifiable).

Format MIMG
Width 96 bits
Opcode 60
Identifier 0x0000000000000000E40F0000

Operands

  • VDATA
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • RSRC
    Read. Any scalar GPR operand including VCC and NULL. Data format: 256-bit image resource constant. (OPR_SREG, FMT_IMG)
  • SAMP
    Read. Any scalar GPR operand including VCC and NULL. Data format: 128-bit image sampler constant. (OPR_SREG, FMT_SAMP)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VSAMPLE encoding (AMD RDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Image / Texture Memory

Reference

AMDGPU / GFX ISA

Description

Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF, user offsets, 16-bit derivatives are provided by the address registers.

Example

image_sample_c_d_o_g16 v[5:6], v[1:5], s[8:15], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11_asm_mimg.s). Not from an AMD document, and not authored here.

Sources