image_sample_c_cd_cl_g16 GPU Native ISA AMD Vector

Image / Texture Memory

image_sample_c_cd_cl_g16

Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (MIMG) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format MIMG

Operands

  • VDATA
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • VADDR
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: N/A (OPR_VGPR, FMT_NUM_F32)
  • SRSRC
    Read. N/A Data format: 256-bit image resource constant. (OPR_SREG_NONULL, FMT_IMG)
  • SSAMP
    Read. N/A Data format: 128-bit image sampler constant. (OPR_SREG_NONULL, FMT_SAMP)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_MIMG encoding (AMD RDNA 2).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Image / Texture Memory

Reference

AMDGPU / GFX ISA

Description

Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF, coarse derivatives, LOD clamp, 16-bit derivatives are provided by the address registers.

Example

image_sample_c_cd_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx10_asm_mimg.s). Not from an AMD document, and not authored here.

Sources