image_load_pck2 GPU Native ISA AMD Vector

Image / Texture Memory

image_load_pck2

Load 2 horizontal elements from the largest miplevel in an image surface and store the result into a vector register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (MIMG) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format MIMG

Operands

  • VDATA
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • VADDR
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • SRSRC
    Read. N/A Data format: 256-bit image resource constant. (OPR_SREG_NONULL, FMT_IMG)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_MIMG encoding (AMD RDNA 2).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Image / Texture Memory

Reference

AMDGPU / GFX ISA

Description

Load 2 horizontal elements from the largest miplevel in an image surface and store the result into a vector register. 8- and 16-bit components are zero-extended. The format specified in the resource descriptor is ignored. Illegal for element sizes greater than 64 bits. No sampling is performed.

Sources