image_gather4h_pck GPU Native ISA AMD Vector

Image / Texture Memory

image_gather4h_pck

Gather all components of 4 texels from a 4x1 row vector on an image surface.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (MIMG) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format MIMG

Operands

  • VDATA
    Written. N/A Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • VADDR
    Read. N/A Data format: N/A (OPR_VGPR, FMT_NUM_F32)
  • SRSRC
    Read. N/A Data format: 256-bit image resource constant. (OPR_SREG, FMT_IMG)
  • SSAMP
    Read. N/A Data format: 128-bit image sampler constant. (OPR_SREG, FMT_SAMP)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_MIMG encoding (AMD CDNA 1).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Image / Texture Memory

Reference

AMDGPU / GFX ISA

Description

Gather all components of 4 texels from a 4x1 row vector on an image surface. Store the result into vector registers. The DMASK selects how many channels to write.

Sources