image_gather4_b_o GPU Native ISA AMD Vector

Image / Texture Memory

image_gather4_b_o

Gather 4 single-component texels from a 2x2 matrix on an image surface.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (MIMG) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format MIMG

Operands

  • VDATA
    Written. N/A Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • VADDR
    Read. N/A Data format: N/A (OPR_VGPR, FMT_NUM_F32)
  • SRSRC
    Read. N/A Data format: 256-bit image resource constant. (OPR_SREG, FMT_IMG)
  • SSAMP
    Read. N/A Data format: 128-bit image sampler constant. (OPR_SREG, FMT_SAMP)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_MIMG encoding (AMD CDNA 1).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Image / Texture Memory

Reference

AMDGPU / GFX ISA

Description

Gather 4 single-component texels from a 2x2 matrix on an image surface. Store the result into vector registers. The DMASK selects which channel to read from (R, G, B, A) and must only have one bit set to 1. Additional data for LOD bias, user offsets are provided by the address registers.

Example

image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx7_asm_mimg.s). Not from an AMD document, and not authored here.

Sources