image_atomic_rsub GPU Native ISA AMD Vector

Image / Texture Memory

image_atomic_rsub

AMDGPU MIMG vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (MIMG) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format MIMG

Operands

  • 1: VGPR
    Vector general-purpose register, one value per lane. Written v1 in the assembler example.
  • 2: VGPR
    Vector general-purpose register, one value per lane. Written v2 in the assembler example.
  • 3: SGPR range
    Consecutive scalar registers, typically a descriptor. Written s[12:19] with dmask:0x1 unorm in the assembler example.

Register classes read from the LLVM assembler example on this page. No source this site uses names these operands, so no names are given.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Image / Texture Memory

Reference

AMDGPU / GFX ISA

Example

image_atomic_rsub v1, v2, s[12:19] dmask:0x1 unorm

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx7_asm_mimg.s). Not from an AMD document, and not authored here.

Sources