image_atomic_and GPU Native ISA AMD Vector

IMAGE ATOMIC AND Image / Texture Memory

image_atomic_and

Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in an image surface.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (MIMG) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format MIMG
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Image / Texture Memory

Reference

AMDGPU / GFX ISA

Description

Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in an image surface. Store the original value from image surface into a vector register iff the GLC bit is set.

Example

image_atomic_and v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources