image_atomic_add_flt GPU Native ISA AMD Vector

Image / Texture Memory

image_atomic_add_flt

Add two single-precision float values stored in the data register and a location in an image surface.

Encoding

Binary Layout (AMD RDNA 4)
VADDR3
95:88
VADDR2
87:80
VADDR1
79:72
VADDR0
71:64
VADDR4
63:56
TFE
55
TH
54:52
SCOPE
51:50
RSRC
49:41
unassigned
40
VDATA
39:32
110100
31:26
DMASK
25:22
10000011
21:14
unassigned
13:8
NV
7
A16
6
D16
5
R128
4
unassigned
3
DIM
2:0
 

The ENC_VIMAGE layout from AMD's machine-readable ISA specification (AMD RDNA 4). Opcode 131 in OP rebuilds 0x0000000000000000D020C000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. No other generation in the specification defines this instruction.

Format MIMG
Width 96 bits
Opcode 131
Identifier 0x0000000000000000D020C000

Operands

  • VDATA
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • RSRC
    Read. Any scalar GPR operand including VCC and NULL. Data format: 256-bit image resource constant. (OPR_SREG, FMT_IMG)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VIMAGE encoding (AMD RDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Image / Texture Memory

Reference

AMDGPU / GFX ISA

Description

Add two single-precision float values stored in the data register and a location in an image surface. Store the original value from image surface into a vector register iff the temporal hint enables atomic return.

Example

image_atomic_add_flt v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx12_asm_vimage.s). Not from an AMD document, and not authored here.

Sources