image_bvh_intersect_ray GPU Native ISA AMD Vector

Image / Texture Memory

image_bvh_intersect_ray

Test the intersection of rays with either box nodes or triangle nodes within a bounded volume hierarchy using 32 bit node pointers.

Also written as bvh_intersect_ray. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD RDNA 4)
VADDR3
95:88
VADDR2
87:80
VADDR1
79:72
VADDR0
71:64
VADDR4
63:56
TFE
55
TH
54:52
SCOPE
51:50
RSRC
49:41
unassigned
40
VDATA
39:32
110100
31:26
DMASK
25:22
00011001
21:14
unassigned
13:8
NV
7
A16
6
D16
5
R128
4
unassigned
3
DIM
2:0
 

The ENC_VIMAGE layout from AMD's machine-readable ISA specification (AMD RDNA 4). Opcode 25 in OP rebuilds 0x0000000000000000D0064000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD RDNA 3.5 (encoding ENC_MIMG, field layout), AMD RDNA 3 (encoding ENC_MIMG, field layout), AMD RDNA 2 (layout not verifiable).

Format MIMG
Width 96 bits
Opcode 25
Identifier 0x0000000000000000D0064000

Operands

  • VDATA
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • RSRC
    Read. Any scalar GPR operand including VCC and NULL. Data format: 128-bit BVH resource constant. (OPR_SREG, FMT_IMG_BVH)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VIMAGE encoding (AMD RDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Image / Texture Memory

Reference

AMDGPU / GFX ISA

Description

Test the intersection of rays with either box nodes or triangle nodes within a bounded volume hierarchy using 32 bit node pointers. Store the results of the test into a vector register. This instruction does not take a sampler constant.

Example

image_bvh_intersect_ray v[5:8], v[1:11], s[8:11]

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources