image_atomic_fcmpswap GPU Native ISA AMD Vector

Image / Texture Memory

image_atomic_fcmpswap

Compare two single-precision float values stored in the data comparison register and a location in an image surface.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (MIMG) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format MIMG

Operands

  • VDATA
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: N/A (OPR_VGPR, FMT_NUM_F32)
  • VADDR
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • SRSRC
    Read. N/A Data format: 256-bit image resource constant. (OPR_SREG_NONULL, FMT_IMG)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_MIMG encoding (AMD RDNA 2).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Image / Texture Memory

Reference

AMDGPU / GFX ISA

Description

Compare two single-precision float values stored in the data comparison register and a location in an image surface. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from image surface into a vector register iff the GLC bit is set.

Example

image_atomic_fcmpswap v[1:2], v2, s[12:19] dmask:0x3 unorm

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx7_asm_mimg.s). Not from an AMD document, and not authored here.

Sources