lds_direct_load GPU Native ISA AMD Vector

LDS Direct / Parameter Fetch

lds_direct_load

Read a single 32-bit value from LDS to all lanes.

Also written as ds_direct_load. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD RDNA 3.5)
11001110
31:24
unassigned
23:22
01
21:20
WAIT_VDST
19:16
ATTR
15:10
ATTR_CHAN
9:8
VDST
7:0
 

The ENC_LDSDIR layout from AMD's machine-readable ISA specification (AMD RDNA 3.5). Opcode 1 in OP rebuilds 0xCE100000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. The same in AMD RDNA 3.

Format DSDIR
Width 32 bits
Opcode 1
Identifier 0xCE100000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_LDSDIR encoding (AMD RDNA 3.5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in LDS Direct / Parameter Fetch

Reference

AMDGPU / GFX ISA

Description

Read a single 32-bit value from LDS to all lanes. A single DWORD is read from LDS memory at ADDR[M0[15:0]], where M0[15:0] is a byte address and is dword-aligned. M0[18:16] specify the data type for the read and may be 0=UBYTE, 1=USHORT, 2=DWORD, 4=SBYTE, 5=SSHORT.

Example

lds_direct_load v17

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources