ds_param_load GPU Native ISA AMD Vector

LDS Direct / Parameter Fetch

ds_param_load

Transfer parameter data from LDS to VGPRs and expand data in LDS using the NewPrimMask (provided in M0) to place per-quad data into lanes 0-3 of each…

Also written as lds_param_load. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD RDNA 4)
11001110
31:24
WAIT_VM_VSRC
23
unassigned
22
00
21:20
WAIT_VA_VDST
19:16
ATTR
15:10
ATTR_CHAN
9:8
VDST
7:0
 

The ENC_VDSDIR layout from AMD's machine-readable ISA specification (AMD RDNA 4). Opcode 0 in OP rebuilds 0xCE000000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. No other generation in the specification defines this instruction.

Format DSDIR
Width 32 bits
Opcode 0
Identifier 0xCE000000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B32)
  • ATTR
    Read. Attribute parameter for interpolation. Data format: 32 bits of arbitrary data. (OPR_ATTR, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VDSDIR encoding (AMD RDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in LDS Direct / Parameter Fetch

Reference

AMDGPU / GFX ISA

Description

Transfer parameter data from LDS to VGPRs and expand data in LDS using the NewPrimMask (provided in M0) to place per-quad data into lanes 0-3 of each quad as follows:

Example

ds_param_load v17, attr32.w

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx12_asm_vdsdir.s). Not from an AMD document, and not authored here.

Sources