ds_direct_load GPU Native ISA AMD Vector

LDS Direct / Parameter Fetch

ds_direct_load

Read a single 32-bit value from LDS to all lanes.

Also written as lds_direct_load. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD RDNA 4)
11001110
31:24
WAIT_VM_VSRC
23
unassigned
22
01
21:20
WAIT_VA_VDST
19:16
ATTR
15:10
ATTR_CHAN
9:8
VDST
7:0
 

The ENC_VDSDIR layout from AMD's machine-readable ISA specification (AMD RDNA 4). Opcode 1 in OP rebuilds 0xCE100000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. No other generation in the specification defines this instruction.

Format DSDIR
Width 32 bits
Opcode 1
Identifier 0xCE100000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VDSDIR encoding (AMD RDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in LDS Direct / Parameter Fetch

Reference

AMDGPU / GFX ISA

Description

Read a single 32-bit value from LDS to all lanes. A single DWORD is read from LDS memory at ADDR[M0[15:0]], where M0[15:0] is a byte address and is dword-aligned. M0[18:16] specify the data type for the read and may be 0=UBYTE, 1=USHORT, 2=DWORD, 4=SBYTE, 5=SSHORT.

Example

ds_direct_load v17

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx12_asm_vdsdir.s). Not from an AMD document, and not authored here.

Sources