lds_param_load GPU Native ISA AMD Vector

LDS Direct / Parameter Fetch

lds_param_load

Transfer parameter data from LDS to VGPRs and expand data in LDS using the NewPrimMask (provided in M0) to place per-quad data into lanes 0-3 of each…

Also written as ds_param_load. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD RDNA 3.5)
11001110
31:24
unassigned
23:22
00
21:20
WAIT_VDST
19:16
ATTR
15:10
ATTR_CHAN
9:8
VDST
7:0
 

The ENC_LDSDIR layout from AMD's machine-readable ISA specification (AMD RDNA 3.5). Opcode 0 in OP rebuilds 0xCE000000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. The same in AMD RDNA 3.

Format DSDIR
Width 32 bits
Opcode 0
Identifier 0xCE000000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B32)
  • ATTR
    Read. Attribute parameter for interpolation. Data format: 32 bits of arbitrary data. (OPR_ATTR, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_LDSDIR encoding (AMD RDNA 3.5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in LDS Direct / Parameter Fetch

Reference

AMDGPU / GFX ISA

Description

Transfer parameter data from LDS to VGPRs and expand data in LDS using the NewPrimMask (provided in M0) to place per-quad data into lanes 0-3 of each quad as follows:

Example

lds_param_load v7, attr2.y wait_vdst:9

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources