AMDGPU / GFX Instructions GPU Native ISA AMD
2442 instructions - showing 100 per page, page 7 of 25 - AMDGPU/GFX is AMD's native, low-level
GPU instruction set family, assembled directly with no virtual intermediate layer. Supported
instructions and their exact encodings vary by GFX compatibility target (e.g.
gfx942, gfx1100). Scalar instructions execute once per wavefront on
the Scalar ALU; vector instructions execute per-lane on the Vector ALU, gated by the EXEC mask.
How AMDGPU compares to the other GPU ISA
Decode a AMDGPU instruction word
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| Mnemonic | Syntax | Format | GFX Targets | Unit | Summary |
|---|---|---|---|---|---|
| global_load_tr_b128 | global_load_tr_b128 | GLOBAL | Load a 16x16 matrix of 16-bit data from the global aperture, transpose data between row-major and column-major order, and store the result into a… | ||
| global_load_tr_b128_w64 | global_load_tr_b128_w64 | GLOBAL | AMDGPU GLOBAL vector instruction operating on b128 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| global_load_tr_b64 | global_load_tr_b64 | GLOBAL | Load a 16x16 matrix of 8-bit data from the global aperture, transpose data between row-major and column-major order, and store the result into a… | ||
| global_load_tr_b64_w64 | global_load_tr_b64_w64 | GLOBAL | AMDGPU GLOBAL vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| global_load_ubyte | global_load_ubyte | GLOBAL | Load 8 bits of unsigned data from the global aperture, zero extend to 32 bits and store the result into a vector register. | ||
| global_load_ubyte_d16 | global_load_ubyte_d16 | GLOBAL | Load 8 bits of unsigned data from the global aperture, zero extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register. | ||
| global_load_ubyte_d16_hi | global_load_ubyte_d16_hi | GLOBAL | Load 8 bits of unsigned data from the global aperture, zero extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register. | ||
| global_load_ushort | global_load_ushort | GLOBAL | Load 16 bits of unsigned data from the global aperture, zero extend to 32 bits and store the result into a vector register. | ||
| global_prefetch_b8 | global_prefetch_b8 | GLOBAL | AMDGPU GLOBAL vector instruction operating on b8 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| global_store_async_from_lds_b128 | global_store_async_from_lds_b128 | GLOBAL | AMDGPU GLOBAL vector instruction operating on b128 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| global_store_async_from_lds_b32 | global_store_async_from_lds_b32 | GLOBAL | AMDGPU GLOBAL vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| global_store_async_from_lds_b64 | global_store_async_from_lds_b64 | GLOBAL | AMDGPU GLOBAL vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| global_store_async_from_lds_b8 | global_store_async_from_lds_b8 | GLOBAL | AMDGPU GLOBAL vector instruction operating on b8 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| global_store_block | global_store_block | GLOBAL | Store a block of data to the global aperture. | ||
| global_store_byte | global_store_byte | GLOBAL | Store 8 bits of data from a vector register into the global aperture. | ||
| global_store_byte_d16_hi | global_store_byte_d16_hi | GLOBAL | Store 8 bits of data from the high 16 bits of a 32-bit vector register into the global aperture. | ||
| global_store_dword | global_store_dword VADDR, VDATA, SADDR, offset | GLOBAL | gfx942, gfx1100 | Vector Memory Unit | Store one 32-bit dword per lane to the global address space using a 64-bit per-lane address. |
| global_store_dword_addtid | global_store_dword_addtid | GLOBAL | Store 32 bits of data from a vector input register into the global aperture. | ||
| global_store_dwordx2 | global_store_dwordx2 | GLOBAL | Store 64 bits of data from vector input registers into the global aperture. | ||
| global_store_dwordx3 | global_store_dwordx3 | GLOBAL | Store 96 bits of data from vector input registers into the global aperture. | ||
| global_store_dwordx4 | global_store_dwordx4 | GLOBAL | Store 128 bits of data from vector input registers into the global aperture. | ||
| global_store_short | global_store_short | GLOBAL | Store 16 bits of data from a vector register into the global aperture. | ||
| global_store_short_d16_hi | global_store_short_d16_hi | GLOBAL | Store 16 bits of data from the high 16 bits of a 32-bit vector register into the global aperture. | ||
| global_wb | global_wb | GLOBAL | Write back dirty cache lines based on the SCOPE field. Increments/decrements STORE_CNT. | ||
| global_wbinv | global_wbinv | GLOBAL | Write back and invalidate cache lines based on the SCOPE field. Increments/decrements STORE_CNT. | ||
| image_atomic_add | image_atomic_add | MIMG | Add two unsigned 32-bit integer values stored in the data register and a location in an image surface. | ||
| image_atomic_add_flt | image_atomic_add_flt | MIMG | Add two single-precision float values stored in the data register and a location in an image surface. | ||
| image_atomic_and | image_atomic_and | MIMG | Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in an image surface. | ||
| image_atomic_cmpswap | image_atomic_cmpswap | MIMG | Compare two unsigned 32-bit integer values stored in the data comparison register and a location in an image surface. | ||
| image_atomic_dec | image_atomic_dec | MIMG | Decrement an unsigned 32-bit integer value from a location in an image surface with wraparound to a value in the data register if the decrement… | ||
| image_atomic_fcmpswap | image_atomic_fcmpswap | MIMG | Compare two single-precision float values stored in the data comparison register and a location in an image surface. | ||
| image_atomic_fmax | image_atomic_fmax | MIMG | Select the maximum of two single-precision float inputs, given two values stored in the data register and a location in an image surface. | ||
| image_atomic_fmin | image_atomic_fmin | MIMG | Select the minimum of two single-precision float inputs, given two values stored in the data register and a location in an image surface. | ||
| image_atomic_inc | image_atomic_inc | MIMG | Increment an unsigned 32-bit integer value from a location in an image surface with wraparound to 0 if the value exceeds a value in the data register. | ||
| image_atomic_max_flt | image_atomic_max_flt | MIMG | Select the IEEE maximumNumber() of two single-precision float inputs, given two values stored in the data register and a location in an image surface. | ||
| image_atomic_max_num_flt | image_atomic_max_num_flt | MIMG | AMDGPU MIMG vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| image_atomic_min_flt | image_atomic_min_flt | MIMG | Select the IEEE minimumNumber() of two single-precision float inputs, given two values stored in the data register and a location in an image surface. | ||
| image_atomic_min_num_flt | image_atomic_min_num_flt | MIMG | AMDGPU MIMG vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| image_atomic_or | image_atomic_or | MIMG | Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in an image surface. | ||
| image_atomic_pk_add_bf16 | image_atomic_pk_add_bf16 | MIMG | Add a packed 2-component BF16 float value from the data register to a location in an image surface. | ||
| image_atomic_pk_add_f16 | image_atomic_pk_add_f16 | MIMG | Add a packed 2-component half-precision float value from the data register to a location in an image surface. | ||
| image_atomic_rsub | image_atomic_rsub | MIMG | AMDGPU MIMG vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| image_atomic_smax | image_atomic_smax | MIMG | Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in an image surface. | ||
| image_atomic_smin | image_atomic_smin | MIMG | Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in an image surface. | ||
| image_atomic_sub | image_atomic_sub | MIMG | Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in an image surface. | ||
| image_atomic_swap | image_atomic_swap | MIMG | Swap an unsigned 32-bit integer value in the data register with a location in an image surface. | ||
| image_atomic_umax | image_atomic_umax | MIMG | Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in an image surface. | ||
| image_atomic_umin | image_atomic_umin | MIMG | Select the minimum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in an image surface. | ||
| image_atomic_xor | image_atomic_xor | MIMG | Calculate bitwise XOR given two unsigned 32-bit integer values stored in the data register and a location in an image surface. | ||
| image_bvh64_intersect_ray | image_bvh64_intersect_ray | MIMG | Test the intersection of rays with either box nodes or triangle nodes within a bounded volume hierarchy using 64 bit node pointers. | ||
| image_bvh8_intersect_ray | image_bvh8_intersect_ray | MIMG | This instruction supports testing one BVH8 node against one ray per lane using both intersection engines. | ||
| image_bvh_dual_intersect_ray | image_bvh_dual_intersect_ray | MIMG | This instruction supports testing two QBVH nodes against the same ray per lane using both intersection engines. | ||
| image_bvh_intersect_ray | image_bvh_intersect_ray | MIMG | Test the intersection of rays with either box nodes or triangle nodes within a bounded volume hierarchy using 32 bit node pointers. | ||
| image_gather4 | image_gather4 | MIMG | Gather 4 single-component texels from a 2x2 matrix on an image surface. | ||
| image_gather4_b | image_gather4_b | MIMG | Gather 4 single-component texels from a 2x2 matrix on an image surface. | ||
| image_gather4_b_cl | image_gather4_b_cl | MIMG | Gather 4 single-component texels from a 2x2 matrix on an image surface. | ||
| image_gather4_b_cl_o | image_gather4_b_cl_o | MIMG | Gather 4 single-component texels from a 2x2 matrix on an image surface. | ||
| image_gather4_b_o | image_gather4_b_o | MIMG | Gather 4 single-component texels from a 2x2 matrix on an image surface. | ||
| image_gather4_c | image_gather4_c | MIMG | Gather 4 single-component texels from a 2x2 matrix on an image surface. | ||
| image_gather4_c_b | image_gather4_c_b | MIMG | Gather 4 single-component texels from a 2x2 matrix on an image surface. | ||
| image_gather4_c_b_cl | image_gather4_c_b_cl | MIMG | Gather 4 single-component texels from a 2x2 matrix on an image surface. | ||
| image_gather4_c_b_cl_o | image_gather4_c_b_cl_o | MIMG | Gather 4 single-component texels from a 2x2 matrix on an image surface. | ||
| image_gather4_c_b_o | image_gather4_c_b_o | MIMG | Gather 4 single-component texels from a 2x2 matrix on an image surface. | ||
| image_gather4_c_cl | image_gather4_c_cl | MIMG | Gather 4 single-component texels from a 2x2 matrix on an image surface. | ||
| image_gather4_c_cl_o | image_gather4_c_cl_o | MIMG | Gather 4 single-component texels from a 2x2 matrix on an image surface. | ||
| image_gather4_c_l | image_gather4_c_l | MIMG | Gather 4 single-component texels from a 2x2 matrix on an image surface. | ||
| image_gather4_c_l_o | image_gather4_c_l_o | MIMG | Gather 4 single-component texels from a 2x2 matrix on an image surface. | ||
| image_gather4_c_lz | image_gather4_c_lz | MIMG | Gather 4 single-component texels from a 2x2 matrix on an image surface. | ||
| image_gather4_c_lz_o | image_gather4_c_lz_o | MIMG | Gather 4 single-component texels from a 2x2 matrix on an image surface. | ||
| image_gather4_c_o | image_gather4_c_o | MIMG | Gather 4 single-component texels from a 2x2 matrix on an image surface. | ||
| image_gather4_cl | image_gather4_cl | MIMG | Gather 4 single-component texels from a 2x2 matrix on an image surface. | ||
| image_gather4_cl_o | image_gather4_cl_o | MIMG | Gather 4 single-component texels from a 2x2 matrix on an image surface. | ||
| image_gather4_l | image_gather4_l | MIMG | Gather 4 single-component texels from a 2x2 matrix on an image surface. | ||
| image_gather4_l_o | image_gather4_l_o | MIMG | Gather 4 single-component texels from a 2x2 matrix on an image surface. | ||
| image_gather4_lz | image_gather4_lz | MIMG | Gather 4 single-component texels from a 2x2 matrix on an image surface. | ||
| image_gather4_lz_o | image_gather4_lz_o | MIMG | Gather 4 single-component texels from a 2x2 matrix on an image surface. | ||
| image_gather4_o | image_gather4_o | MIMG | Gather 4 single-component texels from a 2x2 matrix on an image surface. | ||
| image_gather4h | image_gather4h | MIMG | Gather 4 single-component texels from a 4x1 row vector on an image surface. | ||
| image_gather4h_pck | image_gather4h_pck | MIMG | Gather all components of 4 texels from a 4x1 row vector on an image surface. | ||
| image_gather8h_pck | image_gather8h_pck | MIMG | Gather all components of 8 texels from a 8x1 row vector on an image surface. | ||
| image_get_lod | image_get_lod | MIMG | Return the calculated level of detail (LOD) for the provided input as two single-precision float values. No memory access is performed. | ||
| image_get_resinfo | image_get_resinfo | MIMG | Gather resource information for a given miplevel provided in the address register. | ||
| image_load | image_load | MIMG | Load a texel from the largest miplevel in an image surface and store the result into a vector register. | ||
| image_load_by2 | image_load_by2 | MIMG | Load 2 horizontal elements from the largest miplevel in an image surface and store the result into a vector register. | ||
| image_load_by4 | image_load_by4 | MIMG | Load 4 horizontal elements from the largest miplevel in an image surface and store the result into a vector register. | ||
| image_load_mip | image_load_mip | MIMG | Load a texel from a user-specified miplevel in an image surface and store the result into a vector register. | ||
| image_load_mip_by2 | image_load_mip_by2 | MIMG | Load 2 horizontal elements from a user-specified miplevel in an image surface and store the result into a vector register. | ||
| image_load_mip_by4 | image_load_mip_by4 | MIMG | Load 4 horizontal elements from a user-specified miplevel in an image surface and store the result into a vector register. | ||
| image_load_mip_pck | image_load_mip_pck | MIMG | Load a texel from a user-specified miplevel in an image surface and store the result into a vector register. | ||
| image_load_mip_pck2 | image_load_mip_pck2 | MIMG | Load 2 horizontal elements from a user-specified miplevel in an image surface and store the result into a vector register. | ||
| image_load_mip_pck4 | image_load_mip_pck4 | MIMG | Load 4 horizontal elements from a user-specified miplevel in an image surface and store the result into a vector register. | ||
| image_load_mip_pck_sgn | image_load_mip_pck_sgn | MIMG | Load a texel from a user-specified miplevel in an image surface and store the result into a vector register. | ||
| image_load_pck | image_load_pck | MIMG | Load a texel from the largest miplevel in an image surface and store the result into a vector register. | ||
| image_load_pck2 | image_load_pck2 | MIMG | Load 2 horizontal elements from the largest miplevel in an image surface and store the result into a vector register. | ||
| image_load_pck4 | image_load_pck4 | MIMG | Load 4 horizontal elements from the largest miplevel in an image surface and store the result into a vector register. | ||
| image_load_pck_sgn | image_load_pck_sgn | MIMG | Load a texel from the largest miplevel in an image surface and store the result into a vector register. | ||
| image_msaa_load | image_msaa_load | MIMG | Load up to 4 samples of 1 component from an MSAA resource with a user-specified fragment ID. No sampling is performed. | ||
| image_sample | image_sample | MIMG | Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. | ||
| image_sample_b | image_sample_b | MIMG | Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. | ||
| image_sample_b_cl | image_sample_b_cl | MIMG | Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. |
Source
Normalized from AMD's official ROCm documentation, with the LLVM AMDGPU backend documentation as supplementary compiler-target information. ROCm documentation ↗