AMDGPU / GFX Instructions GPU Native ISA AMD
1960 instructions - showing 100 per page, page 7 of 20 - AMDGPU/GFX is AMD's native, low-level
GPU instruction set family, assembled directly with no virtual intermediate layer. Supported
instructions and their exact encodings vary by GFX compatibility target (e.g.
gfx942, gfx1100). Scalar instructions execute once per wavefront on
the Scalar ALU; vector instructions execute per-lane on the Vector ALU, gated by the EXEC mask.
| Mnemonic | Syntax | Format | GFX Targets | Unit | Summary |
|---|---|---|---|---|---|
| s_and_saveexec_b64 | s_and_saveexec_b64 | SOP1 | gfx1100 | Calculate bitwise AND on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is… | |
| s_andn1_saveexec_b32 | s_andn1_saveexec_b32 | SOP1 | gfx1100 | Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the… | |
| s_andn1_saveexec_b64 | s_andn1_saveexec_b64 | SOP1 | gfx1100 | Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the… | |
| s_andn1_wrexec_b32 | s_andn1_wrexec_b32 | SOP1 | gfx1100 | Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask and also into the scalar… | |
| s_andn1_wrexec_b64 | s_andn1_wrexec_b64 | SOP1 | gfx1100 | Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask and also into the scalar… | |
| s_andn2_b32 | s_andn2_b32 | SOP2 | gfx1100 | Calculate bitwise AND with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is… | |
| s_andn2_b64 | s_andn2_b64 | SOP2 | gfx1100 | Calculate bitwise AND with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is… | |
| s_andn2_saveexec_b32 | s_andn2_saveexec_b32 | SOP1 | gfx1100 | Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the… | |
| s_andn2_saveexec_b64 | s_andn2_saveexec_b64 | SOP1 | gfx1100 | Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the… | |
| s_andn2_wrexec_b32 | s_andn2_wrexec_b32 | SOP1 | gfx1100 | Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask and also into the scalar… | |
| s_andn2_wrexec_b64 | s_andn2_wrexec_b64 | SOP1 | gfx1100 | Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask and also into the scalar… | |
| s_ashr_i32 | s_ashr_i32 | SOP2 | gfx1100 | Given a shift count in the second scalar input, calculate the arithmetic shift right (preserving sign bit) of the first scalar input, store the… | |
| s_ashr_i64 | s_ashr_i64 | SOP2 | gfx1100 | Given a shift count in the second scalar input, calculate the arithmetic shift right (preserving sign bit) of the first scalar input, store the… | |
| s_barrier | s_barrier | SOPP | gfx942, gfx1100 | Scalar ALU | Synchronize all waves of the executing workgroup at this point. |
| s_barrier_init | s_barrier_init | SOP1 | AMDGPU SOP1 scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| s_barrier_join | s_barrier_join | SOP1 | AMDGPU SOP1 scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| s_barrier_leave | s_barrier_leave | SOPP | AMDGPU SOPP scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| s_barrier_signal | s_barrier_signal | SOP1 | Signal that a wave has arrived at a barrier . The argument specifies which barrier to signal. | ||
| s_barrier_signal_isfirst | s_barrier_signal_isfirst | SOP1 | Signal that a wave has arrived at a barrier and set SCC to indicate if this is the first wave to signal the barrier. | ||
| s_barrier_wait | s_barrier_wait | SOPP | Wait for a barrier to complete. The SIMM16 argument specifies which barrier to wait on. | ||
| s_bcnt0_i32_b32 | s_bcnt0_i32_b32 | SOP1 | gfx1100 | Count the number of "0" bits in a scalar input, store the result into a scalar register and set SCC iff the result is nonzero. | |
| s_bcnt0_i32_b64 | s_bcnt0_i32_b64 | SOP1 | gfx1100 | Count the number of "0" bits in a scalar input, store the result into a scalar register and set SCC iff the result is nonzero. | |
| s_bcnt1_i32_b32 | s_bcnt1_i32_b32 | SOP1 | gfx1100 | Count the number of "1" bits in a scalar input, store the result into a scalar register and set SCC iff the result is nonzero. | |
| s_bcnt1_i32_b64 | s_bcnt1_i32_b64 | SOP1 | gfx1100 | Count the number of "1" bits in a scalar input, store the result into a scalar register and set SCC iff the result is nonzero. | |
| s_bfe_i32 | s_bfe_i32 | SOP2 | gfx1100 | Extract a signed bitfield from the first input using field offset and size encoded in the second input, store the result into a scalar register and… | |
| s_bfe_i64 | s_bfe_i64 | SOP2 | gfx1100 | Extract a signed bitfield from the first input using field offset and size encoded in the second input, store the result into a scalar register and… | |
| s_bfe_u32 | s_bfe_u32 | SOP2 | gfx1100 | Extract an unsigned bitfield from the first input using field offset and size encoded in the second input, store the result into a scalar register… | |
| s_bfe_u64 | s_bfe_u64 | SOP2 | gfx1100 | Extract an unsigned bitfield from the first input using field offset and size encoded in the second input, store the result into a scalar register… | |
| s_bfm_b32 | s_bfm_b32 | SOP2 | gfx1100 | Calculate a bitfield mask given a field offset and size and store the result in a scalar register. | |
| s_bfm_b64 | s_bfm_b64 | SOP2 | gfx1100 | Calculate a bitfield mask given a field offset and size and store the result in a scalar register. | |
| s_bitcmp0_b32 | s_bitcmp0_b32 | SOPC | gfx1100 | Extract a bit from the first scalar input based on an index in the second scalar input, and set SCC to 1 iff the extracted bit is equal to 0. | |
| s_bitcmp0_b64 | s_bitcmp0_b64 | SOPC | gfx1100 | Extract a bit from the first scalar input based on an index in the second scalar input, and set SCC to 1 iff the extracted bit is equal to 0. | |
| s_bitcmp1_b32 | s_bitcmp1_b32 | SOPC | gfx1100 | Extract a bit from the first scalar input based on an index in the second scalar input, and set SCC to 1 iff the extracted bit is equal to 1. | |
| s_bitcmp1_b64 | s_bitcmp1_b64 | SOPC | gfx1100 | Extract a bit from the first scalar input based on an index in the second scalar input, and set SCC to 1 iff the extracted bit is equal to 1. | |
| s_bitreplicate_b64_b32 | s_bitreplicate_b64_b32 | SOP1 | gfx1100 | Substitute each bit of a 32 bit scalar input with two instances of itself and store the result into a 64 bit scalar register. | |
| s_bitset0_b32 | s_bitset0_b32 | SOP1 | gfx1100 | Given a bit offset in a scalar input, set the indicated bit in the destination scalar register to 0. | |
| s_bitset0_b64 | s_bitset0_b64 | SOP1 | gfx1100 | Given a bit offset in a scalar input, set the indicated bit in the destination scalar register to 0. | |
| s_bitset1_b32 | s_bitset1_b32 | SOP1 | gfx1100 | Given a bit offset in a scalar input, set the indicated bit in the destination scalar register to 1. | |
| s_bitset1_b64 | s_bitset1_b64 | SOP1 | gfx1100 | Given a bit offset in a scalar input, set the indicated bit in the destination scalar register to 1. | |
| s_branch | s_branch offset | SOPP | gfx942, gfx1100 | Scalar ALU | Unconditional relative branch. |
| s_brev_b32 | s_brev_b32 | SOP1 | gfx1100 | Reverse the order of bits in a scalar input and store the result into a scalar register. | |
| s_brev_b64 | s_brev_b64 | SOP1 | gfx1100 | Reverse the order of bits in a scalar input and store the result into a scalar register. | |
| s_buffer_prefetch_data | s_buffer_prefetch_data | SMEM | Prefetch data into the scalar data cache, relative to a base address provided in a resource descriptor constant. | ||
| s_call_i64 | s_call_i64 | SOPK | gfx1100 | AMDGPU SOPK scalar instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | |
| s_cbranch_join | s_cbranch_join | SOP1 | Conditional branch join point (end of conditional branch block). | ||
| s_cbranch_scc1 | s_cbranch_scc1 offset | SOPP | gfx942, gfx1100 | Scalar ALU | Conditional relative branch, taken when the SCC (scalar condition code) flag is set. |
| s_ceil_f16 | s_ceil_f16 | SOP1 | gfx1100 | Round the half-precision float input up to next integer and store the result in floating point format into a scalar register. | |
| s_ceil_f32 | s_ceil_f32 | SOP1 | gfx1100 | Round the single-precision float input up to next integer and store the result in floating point format into a scalar register. | |
| s_cls_i32 | s_cls_i32 | SOP1 | gfx1100 | Count the number of leading bits that are the same as the sign bit of a scalar input and store the result into a scalar register. | |
| s_cls_i32_i64 | s_cls_i32_i64 | SOP1 | gfx1100 | Count the number of leading bits that are the same as the sign bit of a scalar input and store the result into a scalar register. | |
| s_clz_i32_u32 | s_clz_i32_u32 | SOP1 | gfx1100 | Count the number of leading "0" bits before the first "1" in a scalar input and store the result into a scalar register. | |
| s_clz_i32_u64 | s_clz_i32_u64 | SOP1 | gfx1100 | Count the number of leading "0" bits before the first "1" in a scalar input and store the result into a scalar register. | |
| s_cmov_b32 | s_cmov_b32 | SOP1 | gfx1100 | Move scalar input into a scalar register iff SCC is nonzero. | |
| s_cmov_b64 | s_cmov_b64 | SOP1 | gfx1100 | Move scalar input into a scalar register iff SCC is nonzero. | |
| s_cmovk_i32 | s_cmovk_i32 | SOPK | gfx1100 | Move the sign extension of a literal 16-bit constant into a scalar register iff SCC is nonzero. | |
| s_cmp_eq_f16 | s_cmp_eq_f16 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is equal to the second scalar input. | |
| s_cmp_eq_f32 | s_cmp_eq_f32 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is equal to the second scalar input. | |
| s_cmp_eq_i32 | s_cmp_eq_i32 S0, S1 | SOPC | gfx942, gfx1100 | Scalar ALU | Scalar signed-32-bit equality compare, result written to SCC. |
| s_cmp_eq_u32 | s_cmp_eq_u32 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is equal to the second scalar input. | |
| s_cmp_eq_u64 | s_cmp_eq_u64 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is equal to the second scalar input. | |
| s_cmp_ge_f16 | s_cmp_ge_f16 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is greater than or equal to the second scalar input. | |
| s_cmp_ge_f32 | s_cmp_ge_f32 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is greater than or equal to the second scalar input. | |
| s_cmp_ge_i32 | s_cmp_ge_i32 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is greater than or equal to the second scalar input. | |
| s_cmp_ge_u32 | s_cmp_ge_u32 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is greater than or equal to the second scalar input. | |
| s_cmp_gt_f16 | s_cmp_gt_f16 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is greater than the second scalar input. | |
| s_cmp_gt_f32 | s_cmp_gt_f32 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is greater than the second scalar input. | |
| s_cmp_gt_i32 | s_cmp_gt_i32 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is greater than the second scalar input. | |
| s_cmp_gt_u32 | s_cmp_gt_u32 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is greater than the second scalar input. | |
| s_cmp_le_f16 | s_cmp_le_f16 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is less than or equal to the second scalar input. | |
| s_cmp_le_f32 | s_cmp_le_f32 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is less than or equal to the second scalar input. | |
| s_cmp_le_i32 | s_cmp_le_i32 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is less than or equal to the second scalar input. | |
| s_cmp_le_u32 | s_cmp_le_u32 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is less than or equal to the second scalar input. | |
| s_cmp_lg_f16 | s_cmp_lg_f16 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is less than or greater than the second scalar input. | |
| s_cmp_lg_f32 | s_cmp_lg_f32 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is less than or greater than the second scalar input. | |
| s_cmp_lg_i32 | s_cmp_lg_i32 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is less than or greater than the second scalar input. | |
| s_cmp_lg_u32 | s_cmp_lg_u32 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is less than or greater than the second scalar input. | |
| s_cmp_lg_u64 | s_cmp_lg_u64 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is less than or greater than the second scalar input. | |
| s_cmp_lt_f16 | s_cmp_lt_f16 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is less than the second scalar input. | |
| s_cmp_lt_f32 | s_cmp_lt_f32 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is less than the second scalar input. | |
| s_cmp_lt_i32 | s_cmp_lt_i32 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is less than the second scalar input. | |
| s_cmp_lt_u32 | s_cmp_lt_u32 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is less than the second scalar input. | |
| s_cmp_neq_f16 | s_cmp_neq_f16 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is not equal to the second scalar input. | |
| s_cmp_neq_f32 | s_cmp_neq_f32 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is not equal to the second scalar input. | |
| s_cmp_nge_f16 | s_cmp_nge_f16 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is not greater than or equal to the second scalar input. | |
| s_cmp_nge_f32 | s_cmp_nge_f32 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is not greater than or equal to the second scalar input. | |
| s_cmp_ngt_f16 | s_cmp_ngt_f16 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is not greater than the second scalar input. | |
| s_cmp_ngt_f32 | s_cmp_ngt_f32 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is not greater than the second scalar input. | |
| s_cmp_nle_f16 | s_cmp_nle_f16 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is not less than or equal to the second scalar input. | |
| s_cmp_nle_f32 | s_cmp_nle_f32 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is not less than or equal to the second scalar input. | |
| s_cmp_nlg_f16 | s_cmp_nlg_f16 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is not less than or greater than the second scalar input. | |
| s_cmp_nlg_f32 | s_cmp_nlg_f32 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is not less than or greater than the second scalar input. | |
| s_cmp_nlt_f16 | s_cmp_nlt_f16 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is not less than the second scalar input. | |
| s_cmp_nlt_f32 | s_cmp_nlt_f32 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is not less than the second scalar input. | |
| s_cmp_o_f16 | s_cmp_o_f16 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is orderable to the second scalar input. | |
| s_cmp_o_f32 | s_cmp_o_f32 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is orderable to the second scalar input. | |
| s_cmp_u_f16 | s_cmp_u_f16 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is not orderable to the second scalar input. | |
| s_cmp_u_f32 | s_cmp_u_f32 | SOPC | gfx1100 | Set SCC to 1 iff the first scalar input is not orderable to the second scalar input. | |
| s_cmpk_eq_i32 | s_cmpk_eq_i32 | SOPK | gfx1100 | Set SCC to 1 iff scalar input is equal to the sign extension of a literal 16-bit constant. | |
| s_cmpk_eq_u32 | s_cmpk_eq_u32 | SOPK | gfx1100 | Set SCC to 1 iff scalar input is equal to the zero extension of a literal 16-bit constant. | |
| s_cmpk_ge_i32 | s_cmpk_ge_i32 | SOPK | gfx1100 | Set SCC to 1 iff scalar input is greater than or equal to the sign extension of a literal 16-bit constant. |
Source
Normalized from AMD's official ROCm documentation, with the LLVM AMDGPU backend documentation as supplementary compiler-target information. ROCm documentation ↗