global_store_dwordx3 GPU Native ISA AMD Vector

Vector/Global Memory

global_store_dwordx3

Store 96 bits of data from vector input registers into the global aperture.

Also written as global_store_b96. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (GLOBAL) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format GLOBAL

Operands

  • ADDR
    Read. N/A Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • DATA
    Read. N/A Data format: Value can be anything. (OPR_VGPR_OR_ACCVGPR, FMT_ANY)
  • SADDR
    Read. N/A Data format: Value can be anything. (OPR_SREG, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_FLAT_GLBL encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector/Global Memory

Reference

AMDGPU / GFX ISA

Semantics

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32); MEM[addr].b32 = VDATA[31 : 0]; MEM[addr + 4U].b32 = VDATA[63 : 32]; MEM[addr + 8U].b32 = VDATA[95 : 64]

Example

global_store_dwordx3 v1, v[2:4], vcc

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources