global_load_dwordx2 GPU Native ISA AMD Vector
GLOBAL LOAD DWORDX2 Vector/Global Memory
global_load_dwordx2
Load 64 bits of data from the global aperture into a vector register.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (GLOBAL)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
Per-target GFX compatibility has not yet been verified for this instruction.
Related
More in Vector/Global Memory
Reference
AMDGPU / GFX ISA
Semantics
addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
VDATA[31 : 0] = MEM[addr].b32;
VDATA[63 : 32] = MEM[addr + 4U].b32
Example
global_load_dwordx2 v[5:6], v1, vccA real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 504. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project