global_load_dword_addtid GPU Native ISA AMD Vector

Vector/Global Memory

global_load_dword_addtid

Load 32 bits of data from the global aperture into a vector register.

Also written as global_load_addtid_b32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (GLOBAL) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format GLOBAL

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • SADDR
    Read. N/A Data format: Value can be anything. (OPR_SREG, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_FLAT_GLBL encoding (AMD RDNA 2).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector/Global Memory

Reference

AMDGPU / GFX ISA

Description

Load 32 bits of data from the global aperture into a vector register. The memory base address is provided in a scalar register and the lane ID is used as an offset.

Example

global_load_dword_addtid v1, off offset:16

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx1030_new.s). Not from an AMD document, and not authored here.

Sources