global_inv GPU Native ISA AMD Vector

Vector/Global Memory

global_inv

Invalidate cache lines based on the SCOPE field. Increments/decrements LOAD_CNT.

Encoding

Binary Layout (AMD CDNA 5)
IOFFSET
95:72
VADDR
71:64
unassigned
63
VSRC
62:55
TH
54:52
SCOPE
51:50
SVE
49
SCALE_OFFSET
48
unassigned
47:40
VDST
39:32
11101110
31:24
unassigned
23:22
00101011
21:14
unassigned
13:8
NV
7
SADDR
6:0
 

The ENC_VGLOBAL layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 43 in OP rebuilds 0x0000000000000000EE0AC000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD RDNA 4 (field layout).

Format GLOBAL
Width 96 bits
Opcode 43
Identifier 0x0000000000000000EE0AC000

Operands

  • 1: modifier
    Assembler modifier or optional field rather than a register. Written scope:SCOPE_DEV in the assembler example.

Register classes read from the LLVM assembler example on this page. No source this site uses names these operands, so no names are given.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector/Global Memory

Reference

AMDGPU / GFX ISA

Example

global_inv scope:SCOPE_DEV

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx12_asm_vflat.s). Not from an AMD document, and not authored here.

Sources