global_atomic_ordered_add_b64 GPU Native ISA AMD Vector

Vector/Global Memory

global_atomic_ordered_add_b64

Given an (ID, value) pair in memory, increment the value by a given amount if the ID matches an ID provided by the shader.

Encoding

Binary Layout (AMD RDNA 4)
IOFFSET
95:72
VADDR
71:64
unassigned
63
VSRC
62:55
TH
54:52
SCOPE
51:50
SVE
49
unassigned
48:40
VDST
39:32
11101110
31:24
unassigned
23:22
01110011
21:14
unassigned
13:8
NV
7
SADDR
6:0
 

The ENC_VGLOBAL layout from AMD's machine-readable ISA specification (AMD RDNA 4). Opcode 115 in OP rebuilds 0x0000000000000000EE1CC000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. No other generation in the specification defines this instruction.

Format GLOBAL
Width 96 bits
Opcode 115
Identifier 0x0000000000000000EE1CC000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • VADDR
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • VSRC
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • SADDR
    Read. Any scalar GPR operand including VCC and NULL. Data format: Value can be anything. (OPR_SREG, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VGLOBAL encoding (AMD RDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector/Global Memory

Reference

AMDGPU / GFX ISA

Example

global_atomic_ordered_add_b64 v0, v[2:3], s[0:1] offset:64

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx12_asm_vflat.s). Not from an AMD document, and not authored here.

Sources