global_atomic_inc_x2 GPU Native ISA AMD Vector

GLOBAL ATOMIC INC X2 Vector/Global Memory

global_atomic_inc_x2

Increment an unsigned 64-bit integer value from a location in the global aperture with wraparound to 0 if the value exceeds a value in the data…

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (GLOBAL) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format GLOBAL
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector/Global Memory

Reference

AMDGPU / GFX ISA

Description

Increment an unsigned 64-bit integer value from a location in the global aperture with wraparound to 0 if the value exceeds a value in the data register. Store the original value from global aperture into a vector register iff the SC0 bit is set.

Semantics

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32); tmp = MEM[addr].u64; src = DATA.u64; MEM[addr].u64 = tmp >= src ? 0ULL : tmp + 1ULL; RETURN_DATA.u64 = tmp

Example

global_atomic_inc_x2 v1, v[2:3], vcc

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources