global_atomic_inc GPU Native ISA AMD Vector
GLOBAL ATOMIC INC Vector/Global Memory
global_atomic_inc
Increment an unsigned 32-bit integer value from a location in the global aperture with wraparound to 0 if the value exceeds a value in the data…
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (GLOBAL)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
Per-target GFX compatibility has not yet been verified for this instruction.
Related
More in Vector/Global Memory
Reference
AMDGPU / GFX ISA
Description
Increment an unsigned 32-bit integer value from a location in the global aperture with wraparound to 0 if the value exceeds a value in the data register. Store the original value from global aperture into a vector register iff the SC0 bit is set.
Semantics
addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].u32;
src = DATA.u32;
MEM[addr].u32 = tmp >= src ? 0U : tmp + 1U;
RETURN_DATA.u32 = tmp
Example
global_atomic_inc v1, v2, vccA real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 511. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project