global_atomic_add_x2 GPU Native ISA AMD Vector
GLOBAL ATOMIC ADD X2 Vector/Global Memory
global_atomic_add_x2
Add two unsigned 64-bit integer values stored in the data register and a location in the global aperture.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (GLOBAL)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
Per-target GFX compatibility has not yet been verified for this instruction.
Related
More in Vector/Global Memory
Reference
AMDGPU / GFX ISA
Description
Add two unsigned 64-bit integer values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.
Semantics
addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32);
tmp = MEM[addr].u64;
MEM[addr].u64 += DATA.u64;
RETURN_DATA.u64 = tmp
Example
global_atomic_add_x2 v1, v[2:3], vccA real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 514. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project