global_atomic_fcmpswap_x2 GPU Native ISA AMD Vector

Vector/Global Memory

global_atomic_fcmpswap_x2

Compare two double-precision float values stored in the data comparison register and a location in the global aperture.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (GLOBAL) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format GLOBAL

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: N/A (OPR_VGPR, FMT_NUM_F64)
  • ADDR
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • DATA
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • SADDR
    Read. N/A Data format: Value can be anything. (OPR_SREG, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_FLAT_GLBL encoding (AMD RDNA 2).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector/Global Memory

Reference

AMDGPU / GFX ISA

Description

Compare two double-precision float values stored in the data comparison register and a location in the global aperture. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from global aperture into a vector register iff the GLC bit is set.

Example

global_atomic_fcmpswap_x2 v[1:2], v[2:5], off offset:-1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx10_asm_flat.s). Not from an AMD document, and not authored here.

Sources