global_atomic_add_f64 GPU Native ISA AMD Vector

Vector/Global Memory

global_atomic_add_f64

Add a double-precision float value in the data register to a location in the global aperture.

Encoding

Binary Layout (AMD CDNA 5)
IOFFSET
95:72
VADDR
71:64
unassigned
63
VSRC
62:55
TH
54:52
SCOPE
51:50
SVE
49
SCALE_OFFSET
48
unassigned
47:40
VDST
39:32
11101110
31:24
unassigned
23:22
01010101
21:14
unassigned
13:8
NV
7
SADDR
6:0
 

The ENC_VGLOBAL layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 85 in OP rebuilds 0x0000000000000000EE154000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 4 (layout not verifiable), AMD CDNA 3 (layout not verifiable), AMD CDNA 2 (layout not verifiable).

Format GLOBAL
Width 96 bits
Opcode 85
Identifier 0x0000000000000000EE154000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • VADDR
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • VSRC
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • SADDR
    Read. Any scalar GPR operand including VCC and NULL. Data format: Value can be anything. (OPR_SREG, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VGLOBAL encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx942✅ Supported

Floating-point addition handles NAN/INF/denorm.

Related

More in Vector/Global Memory

Reference

AMDGPU / GFX ISA

Description

Add a double-precision float value in the data register to a location in the global aperture. Store the original value from global aperture into a vector register iff the SC0 bit is set.

Semantics

tmp = MEM[ADDR].f64; MEM[ADDR].f64 += DATA.f64; RETURN_DATA = tmp

Sources