global_load_sbyte_d16 GPU Native ISA AMD Vector

Vector/Global Memory

global_load_sbyte_d16

Load 8 bits of signed data from the global aperture, sign extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.

Also written as global_load_d16_i8. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (GLOBAL) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format GLOBAL

Operands

  • VDST
    Written. N/A Data format: Value can be anything. (OPR_VGPR_OR_ACCVGPR, FMT_ANY)
  • ADDR
    Read. N/A Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • SADDR
    Read. N/A Data format: Value can be anything. (OPR_SREG, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_FLAT_GLBL encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector/Global Memory

Reference

AMDGPU / GFX ISA

Semantics

addr = CalcGlobalAddr(ADDR.b32, SADDR.b32, OFFSET.b32); VDATA[15 : 0].i16 = 16'I(signext(MEM[addr].i8)); // VDATA[31:16] is preserved.

Example

global_load_sbyte_d16 v5, v1, s[4:5]

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx9_asm_flat.s). Not from an AMD document, and not authored here.

Sources